Commit 6df82a7b authored Jun 09, 2016 by James Hogan Committed by Paolo Bonzini Jun 14, 2016

MIPS: KVM: Fix CACHE triggered exception emulation



When emulating TLB miss / invalid exceptions during CACHE instruction
emulation, be sure to set up the correct PC and host_cp0_badvaddr state
for the kvm_mips_emlulate_tlb*_ld() function to pick up for guest EPC
and BadVAddr.

PC needs to be rewound otherwise the guest EPC will end up pointing at
the next instruction after the faulting CACHE instruction.

host_cp0_badvaddr must be set because guest CACHE instructions trap with
a Coprocessor Unusable exception, which doesn't update the host BadVAddr
as a TLB exception would.

This doesn't tend to get hit when dynamic translation of emulated
instructions is enabled, since only the first execution of each CACHE
instruction actually goes through this code path, with subsequent
executions hitting the SYNCI instruction that it gets replaced with.

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Cc: Radim Krčmář <rkrcmar@redhat.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: kvm@vger.kernel.org
Cc: linux-mips@linux-mips.org
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

parent cc81e948

arch/mips/kvm/emulate.c

+3 −0

Original line number	Diff line number	Diff line
		@@ -1636,6 +1636,7 @@ enum emulation_result kvm_mips_emulate_cache(uint32_t inst, uint32_t *opc,
		if (index < 0) {
		vcpu->arch.host_cp0_entryhi = (va & VPN2_MASK);
		vcpu->arch.host_cp0_badvaddr = va;
		vcpu->arch.pc = curr_pc;
		er = kvm_mips_emulate_tlbmiss_ld(cause, NULL, run,
		vcpu);
		preempt_enable();
		@@ -1647,6 +1648,8 @@ enum emulation_result kvm_mips_emulate_cache(uint32_t inst, uint32_t *opc,
		* invalid exception to the guest
		*/
		if (!TLB_IS_VALID(*tlb, va)) {
		vcpu->arch.host_cp0_badvaddr = va;
		vcpu->arch.pc = curr_pc;
		er = kvm_mips_emulate_tlbinv_ld(cause, NULL,
		run, vcpu);
		preempt_enable();

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