Commit 6df383cf authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge branch 'drm-next-4.10' of git://people.freedesktop.org/~agd5f/linux into drm-fixes 

- fix display regression on DCE6/8
- Powergating fixes for GFX8
- amdgpu SI fixes (golden settings, proper rev id setup, etc.)

* 'drm-next-4.10' of git://people.freedesktop.org/~agd5f/linux: (21 commits)
  drm/amdgpu: update tile table for oland/hainan
  drm/amdgpu: update tile table for verde
  drm/amdgpu: update rev id for verde
  drm/amdgpu: update golden setting for verde
  drm/amdgpu: update rev id for oland
  drm/amdgpu: update golden setting for oland
  drm/amdgpu: update rev id for hainan
  drm/amdgpu: update golden setting for hainan
  drm/amdgpu: update rev id for pitcairn
  drm/amdgpu: update golden setting for pitcairn
  drm/amdgpu: update golden setting/tiling table of tahiti
  drm/amdgpu: fix cursor setting of dce6/dce8
  drm/amdgpu: refine set clock gating for tonga/polaris
  drm/amdgpu: initialize cg flags for tonga/polaris10/polaris11.
  drm/amdgpu: add new gfx cg flags.
  drm/amdgpu: fix pg can't be disabled by PG mask.
  drm/amdgpu: always initialize gfx pg for gfx_v8.0.
  drm/amdgpu: enable AMD_PG_SUPPORT_CP in Carrizo/Stoney.
  drm/amdgpu: fix init save/restore list in gfx_v8.0
  drm/amdgpu: fix enable_cp_power_gating in gfx_v8.0.
  ...
parents 50f6584e f8d9422e

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

+1 −5
Original line number Diff line number Diff line
@@ -1944,9 +1944,7 @@ static int dce_v6_0_crtc_cursor_set2(struct drm_crtc *crtc, 


	dce_v6_0_lock_cursor(crtc, true);



	if (width != amdgpu_crtc->cursor_width ||

	    height != amdgpu_crtc->cursor_height ||

	    hot_x != amdgpu_crtc->cursor_hot_x ||

	if (hot_x != amdgpu_crtc->cursor_hot_x ||

	    hot_y != amdgpu_crtc->cursor_hot_y) {

		int x, y;
@@ -1955,8 +1953,6 @@ static int dce_v6_0_crtc_cursor_set2(struct drm_crtc *crtc, 


		dce_v6_0_cursor_move_locked(crtc, x, y);



		amdgpu_crtc->cursor_width = width;

		amdgpu_crtc->cursor_height = height;

		amdgpu_crtc->cursor_hot_x = hot_x;

		amdgpu_crtc->cursor_hot_y = hot_y;

	}

drivers/gpu/drm/amd/amdgpu/dce_v8_0.c

+0 −2
Original line number Diff line number Diff line
@@ -2438,8 +2438,6 @@ static int dce_v8_0_crtc_cursor_set2(struct drm_crtc *crtc, 


		dce_v8_0_cursor_move_locked(crtc, x, y);



		amdgpu_crtc->cursor_width = width;

		amdgpu_crtc->cursor_height = height;

		amdgpu_crtc->cursor_hot_x = hot_x;

		amdgpu_crtc->cursor_hot_y = hot_y;

	}

drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c

+665 −270

File changed.

Preview size limit exceeded, changes collapsed.

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

+161 −88
Original line number Diff line number Diff line
@@ -3949,8 +3949,12 @@ static int gfx_v8_0_init_save_restore_list(struct amdgpu_device *adev) 
	temp = mmRLC_SRM_INDEX_CNTL_ADDR_0;

	data = mmRLC_SRM_INDEX_CNTL_DATA_0;

	for (i = 0; i < sizeof(unique_indices) / sizeof(int); i++) {

		amdgpu_mm_wreg(adev, temp + i, unique_indices[i] & 0x3FFFF, false);

		amdgpu_mm_wreg(adev, data + i, unique_indices[i] >> 20, false);

		if (unique_indices[i] != 0) {

			amdgpu_mm_wreg(adev, temp + i,

					unique_indices[i] & 0x3FFFF, false);

			amdgpu_mm_wreg(adev, data + i,

					unique_indices[i] >> 20, false);

		}

	}

	kfree(register_list_format);
@@ -3966,9 +3970,6 @@ static void gfx_v8_0_init_power_gating(struct amdgpu_device *adev) 
{

	uint32_t data;



	if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |

			      AMD_PG_SUPPORT_GFX_SMG |

			      AMD_PG_SUPPORT_GFX_DMG)) {

	WREG32_FIELD(CP_RB_WPTR_POLL_CNTL, IDLE_POLL_COUNT, 0x60);



	data = REG_SET_FIELD(0, RLC_PG_DELAY, POWER_UP_DELAY, 0x10);
@@ -3979,7 +3980,7 @@ static void gfx_v8_0_init_power_gating(struct amdgpu_device *adev) 


	WREG32_FIELD(RLC_PG_DELAY_2, SERDES_CMD_DELAY, 0x3);

	WREG32_FIELD(RLC_AUTO_PG_CTRL, GRBM_REG_SAVE_GFX_IDLE_THRESHOLD, 0x55f0);

	}



}



static void cz_enable_sck_slow_down_on_power_up(struct amdgpu_device *adev,
@@ -3996,23 +3997,16 @@ static void cz_enable_sck_slow_down_on_power_down(struct amdgpu_device *adev, 


static void cz_enable_cp_power_gating(struct amdgpu_device *adev, bool enable)

{

	WREG32_FIELD(RLC_PG_CNTL, CP_PG_DISABLE, enable ? 1 : 0);

	WREG32_FIELD(RLC_PG_CNTL, CP_PG_DISABLE, enable ? 0 : 1);

}



static void gfx_v8_0_init_pg(struct amdgpu_device *adev)

{

	if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |

			      AMD_PG_SUPPORT_GFX_SMG |

			      AMD_PG_SUPPORT_GFX_DMG |

			      AMD_PG_SUPPORT_CP |

			      AMD_PG_SUPPORT_GDS |

			      AMD_PG_SUPPORT_RLC_SMU_HS)) {

	if ((adev->asic_type == CHIP_CARRIZO) ||

	    (adev->asic_type == CHIP_STONEY)) {

		gfx_v8_0_init_csb(adev);

		gfx_v8_0_init_save_restore_list(adev);

		gfx_v8_0_enable_save_restore_machine(adev);



		if ((adev->asic_type == CHIP_CARRIZO) ||

		    (adev->asic_type == CHIP_STONEY)) {

		WREG32(mmRLC_JUMP_TABLE_RESTORE, adev->gfx.rlc.cp_table_gpu_addr >> 8);

		gfx_v8_0_init_power_gating(adev);

		WREG32(mmRLC_PG_ALWAYS_ON_CU_MASK, adev->gfx.cu_info.ao_cu_mask);
@@ -4028,9 +4022,12 @@ static void gfx_v8_0_init_pg(struct amdgpu_device *adev) 
		else

			cz_enable_cp_power_gating(adev, false);

	} else if (adev->asic_type == CHIP_POLARIS11) {

		gfx_v8_0_init_csb(adev);

		gfx_v8_0_init_save_restore_list(adev);

		gfx_v8_0_enable_save_restore_machine(adev);

		gfx_v8_0_init_power_gating(adev);

	}

	}



}



static void gfx_v8_0_rlc_stop(struct amdgpu_device *adev)
@@ -5339,13 +5336,10 @@ static int gfx_v8_0_set_powergating_state(void *handle, 
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	bool enable = (state == AMD_PG_STATE_GATE) ? true : false;



	if (!(adev->pg_flags & AMD_PG_SUPPORT_GFX_PG))

		return 0;



	switch (adev->asic_type) {

	case CHIP_CARRIZO:

	case CHIP_STONEY:

		if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)



		cz_update_gfx_cg_power_gating(adev, enable);



		if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG) && enable)
@@ -5791,25 +5785,49 @@ static int gfx_v8_0_update_gfx_clock_gating(struct amdgpu_device *adev, 
static int gfx_v8_0_tonga_update_gfx_clock_gating(struct amdgpu_device *adev,

					  enum amd_clockgating_state state)

{

	uint32_t msg_id, pp_state;

	uint32_t msg_id, pp_state = 0;

	uint32_t pp_support_state = 0;

	void *pp_handle = adev->powerplay.pp_handle;



	if (adev->cg_flags & (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_CGLS)) {

		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) {

			pp_support_state = PP_STATE_SUPPORT_LS;

			pp_state = PP_STATE_LS;

		}

		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) {

			pp_support_state |= PP_STATE_SUPPORT_CG;

			pp_state |= PP_STATE_CG;

		}

		if (state == AMD_CG_STATE_UNGATE)

			pp_state = 0;

	else

		pp_state = PP_STATE_CG | PP_STATE_LS;



		msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,

				PP_BLOCK_GFX_CG,

			PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,

				pp_support_state,

				pp_state);

		amd_set_clockgating_by_smu(pp_handle, msg_id);

	}



	if (adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS)) {

		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {

			pp_support_state = PP_STATE_SUPPORT_LS;

			pp_state = PP_STATE_LS;

		}



		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) {

			pp_support_state |= PP_STATE_SUPPORT_CG;

			pp_state |= PP_STATE_CG;

		}



		if (state == AMD_CG_STATE_UNGATE)

			pp_state = 0;



		msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,

				PP_BLOCK_GFX_MG,

			PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,

				pp_support_state,

				pp_state);

		amd_set_clockgating_by_smu(pp_handle, msg_id);

	}



	return 0;

}
@@ -5817,43 +5835,98 @@ static int gfx_v8_0_tonga_update_gfx_clock_gating(struct amdgpu_device *adev, 
static int gfx_v8_0_polaris_update_gfx_clock_gating(struct amdgpu_device *adev,

					  enum amd_clockgating_state state)

{

	uint32_t msg_id, pp_state;



	uint32_t msg_id, pp_state = 0;

	uint32_t pp_support_state = 0;

	void *pp_handle = adev->powerplay.pp_handle;



	if (adev->cg_flags & (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_CGLS)) {

		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) {

			pp_support_state = PP_STATE_SUPPORT_LS;

			pp_state = PP_STATE_LS;

		}

		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) {

			pp_support_state |= PP_STATE_SUPPORT_CG;

			pp_state |= PP_STATE_CG;

		}

		if (state == AMD_CG_STATE_UNGATE)

			pp_state = 0;

	else

		pp_state = PP_STATE_CG | PP_STATE_LS;



		msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,

				PP_BLOCK_GFX_CG,

			PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,

				pp_support_state,

				pp_state);

		amd_set_clockgating_by_smu(pp_handle, msg_id);

	}



	if (adev->cg_flags & (AMD_CG_SUPPORT_GFX_3D_CGCG | AMD_CG_SUPPORT_GFX_3D_CGLS)) {

		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) {

			pp_support_state = PP_STATE_SUPPORT_LS;

			pp_state = PP_STATE_LS;

		}

		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) {

			pp_support_state |= PP_STATE_SUPPORT_CG;

			pp_state |= PP_STATE_CG;

		}

		if (state == AMD_CG_STATE_UNGATE)

			pp_state = 0;



		msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,

				PP_BLOCK_GFX_3D,

			PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,

				pp_support_state,

				pp_state);

		amd_set_clockgating_by_smu(pp_handle, msg_id);

	}



	if (adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS)) {

		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {

			pp_support_state = PP_STATE_SUPPORT_LS;

			pp_state = PP_STATE_LS;

		}



		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) {

			pp_support_state |= PP_STATE_SUPPORT_CG;

			pp_state |= PP_STATE_CG;

		}



		if (state == AMD_CG_STATE_UNGATE)

			pp_state = 0;



		msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,

				PP_BLOCK_GFX_MG,

			PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,

				pp_support_state,

				pp_state);

		amd_set_clockgating_by_smu(pp_handle, msg_id);

	}



	if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) {

		pp_support_state = PP_STATE_SUPPORT_LS;



		if (state == AMD_CG_STATE_UNGATE)

			pp_state = 0;

		else

			pp_state = PP_STATE_LS;



		msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,

				PP_BLOCK_GFX_RLC,

			PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,

				pp_support_state,

				pp_state);

		amd_set_clockgating_by_smu(pp_handle, msg_id);

	}



	if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {

		pp_support_state = PP_STATE_SUPPORT_LS;



		if (state == AMD_CG_STATE_UNGATE)

			pp_state = 0;

		else

			pp_state = PP_STATE_LS;

		msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,

			PP_BLOCK_GFX_CP,

			PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,

			pp_support_state,

			pp_state);

		amd_set_clockgating_by_smu(pp_handle, msg_id);

	}



	return 0;

}

drivers/gpu/drm/amd/amdgpu/si.c

+227 −215

File changed.

Preview size limit exceeded, changes collapsed.

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