Commit 6ded416d authored by Jan Kotas's avatar Jan Kotas Committed by Mauro Carvalho Chehab
Browse files

media: Fix Lane mapping in Cadence CSI2TX 



This patch fixes mapping of lanes in DPHY_CFG register
of the controller. In the register, bit 0 means first data lane.
In Linux we currently assume lane 0 is clock.

Signed-off-by: default avatarJan Kotas <jank@cadence.com>
Acked-by: default avatarMaxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: default avatarSakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: default avatarMauro Carvalho Chehab <mchehab+samsung@kernel.org>
parent bf9df90b

drivers/media/platform/cadence/cdns-csi2tx.c

+2 −2
Original line number Diff line number Diff line
@@ -236,7 +236,7 @@ static int csi2tx_start(struct csi2tx_priv *csi2tx) 
	/* Put our lanes (clock and data) out of reset */

	reg = CSI2TX_DPHY_CFG_CLK_RESET | CSI2TX_DPHY_CFG_MODE_LPDT;

	for (i = 0; i < csi2tx->num_lanes; i++)

		reg |= CSI2TX_DPHY_CFG_LANE_RESET(csi2tx->lanes[i]);

		reg |= CSI2TX_DPHY_CFG_LANE_RESET(csi2tx->lanes[i] - 1);

	writel(reg, csi2tx->base + CSI2TX_DPHY_CFG_REG);



	udelay(10);
@@ -244,7 +244,7 @@ static int csi2tx_start(struct csi2tx_priv *csi2tx) 
	/* Enable our (clock and data) lanes */

	reg |= CSI2TX_DPHY_CFG_CLK_ENABLE;

	for (i = 0; i < csi2tx->num_lanes; i++)

		reg |= CSI2TX_DPHY_CFG_LANE_ENABLE(csi2tx->lanes[i]);

		reg |= CSI2TX_DPHY_CFG_LANE_ENABLE(csi2tx->lanes[i] - 1);

	writel(reg, csi2tx->base + CSI2TX_DPHY_CFG_REG);



	udelay(10);

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