Merge tag 'xtensa-20190917' of git://github.com/jcmvbkbc/linux-xtensa (6dec8c15) · Commits · 戴 / test

arch/xtensa/Kconfig

+48 −0

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		@@ -385,6 +385,54 @@ config FAST_SYSCALL_SPILL_REGISTERS

		If unsure, say N.

		config USER_ABI_CALL0
		bool

		choice
		prompt "Userspace ABI"
		default USER_ABI_DEFAULT
		help
		Select supported userspace ABI.

		If unsure, choose the default ABI.

		config USER_ABI_DEFAULT
		bool "Default ABI only"
		help
		Assume default userspace ABI. For XEA2 cores it is windowed ABI.
		call0 ABI binaries may be run on such kernel, but signal delivery
		will not work correctly for them.

		config USER_ABI_CALL0_ONLY
		bool "Call0 ABI only"
		select USER_ABI_CALL0
		help
		Select this option to support only call0 ABI in userspace.
		Windowed ABI binaries will crash with a segfault caused by
		an illegal instruction exception on the first 'entry' opcode.

		Choose this option if you're planning to run only user code
		built with call0 ABI.

		config USER_ABI_CALL0_PROBE
		bool "Support both windowed and call0 ABI by probing"
		select USER_ABI_CALL0
		help
		Select this option to support both windowed and call0 userspace
		ABIs. When enabled all processes are started with PS.WOE disabled
		and a fast user exception handler for an illegal instruction is
		used to turn on PS.WOE bit on the first 'entry' opcode executed by
		the userspace.

		This option should be enabled for the kernel that must support
		both call0 and windowed ABIs in userspace at the same time.

		Note that Xtensa ISA does not guarantee that entry opcode will
		raise an illegal instruction exception on cores with XEA2 when
		PS.WOE is disabled, check whether the target core supports it.

		endchoice

		endmenu

		config XTENSA_CALIBRATE_CCOUNT

arch/xtensa/boot/dts/virt.dts

+4 −4

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		@@ -52,12 +52,12 @@
		#size-cells = <2>;
		#interrupt-cells = <0x1>;

		bus-range = <0x0 0x3f>;
		reg = <0xc0000000 0x04000000>;
		bus-range = <0x0 0x3e>;
		reg = <0xf0100000 0x03f00000>;

		// BUS_ADDRESS(3) CPU_PHYSICAL(1) SIZE(2)
		ranges = <0x01000000 0x0 0xc4000000 0xc4000000 0x0 0x04000000>,
		<0x02000000 0x0 0xc8000000 0xc8000000 0x0 0x18000000>;
		ranges = <0x01000000 0x0 0xf0000000 0xf0000000 0x0 0x00010000>,
		<0x02000000 0x0 0xf4000000 0xf4000000 0x0 0x08000000>;

		// PCI_DEVICE(3) INT#(1) CONTROLLER(PHANDLE) CONTROLLER_DATA(2)
		interrupt-map = <

arch/xtensa/include/asm/io.h

+1 −0

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		@@ -21,6 +21,7 @@

		#define IOADDR(x) (XCHAL_KIO_BYPASS_VADDR + (x))
		#define IO_SPACE_LIMIT ~0
		#define PCI_IOBASE ((void __iomem *)XCHAL_KIO_BYPASS_VADDR)

		#ifdef CONFIG_MMU

arch/xtensa/include/asm/processor.h

+9 −2

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		@@ -176,14 +176,21 @@ struct thread_struct {

		/*
		* Do necessary setup to start up a newly executed thread.
		* Note: We set-up ps as if we did a call4 to the new pc.
		* Note: When windowed ABI is used for userspace we set-up ps
		* as if we did a call4 to the new pc.
		* set_thread_state in signal.c depends on it.
		*/
		#define USER_PS_VALUE ((1 << PS_WOE_BIT) \| \
		#if IS_ENABLED(CONFIG_USER_ABI_CALL0)
		#define USER_PS_VALUE ((USER_RING << PS_RING_SHIFT) \| \
		(1 << PS_UM_BIT) \| \
		(1 << PS_EXCM_BIT))
		#else
		#define USER_PS_VALUE (PS_WOE_MASK \| \
		(1 << PS_CALLINC_SHIFT) \| \
		(USER_RING << PS_RING_SHIFT) \| \
		(1 << PS_UM_BIT) \| \
		(1 << PS_EXCM_BIT))
		#endif

		/* Clearing a0 terminates the backtrace. */
		#define start_thread(regs, new_pc, new_sp) \

arch/xtensa/include/asm/regs.h

+1 −0

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		@@ -81,6 +81,7 @@
		/* PS register fields. */

		#define PS_WOE_BIT 18
		#define PS_WOE_MASK 0x00040000
		#define PS_CALLINC_SHIFT 16
		#define PS_CALLINC_MASK 0x00030000
		#define PS_OWB_SHIFT 8

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