clk: meson: g12a: Prepare the GPU clock tree to change at runtime (6dde0ae3) · Commits · 戴 / test

drivers/clk/meson/g12a.c

+22 −8

Original line number	Diff line number	Diff line
		@@ -3702,7 +3702,9 @@ static struct clk_regmap g12a_hdmi = {

		/*
		* The MALI IP is clocked by two identical clocks (mali_0 and mali_1)
		* muxed by a glitch-free switch.
		* muxed by a glitch-free switch. The CCF can manage this glitch-free
		* mux because it does top-to-bottom updates the each clock tree and
		* switches to the "inactive" one when CLK_SET_RATE_GATE is set.
		*/
		static const struct clk_parent_data g12a_mali_0_1_parent_data[] = {
		{ .fw_name = "xtal", },
		@@ -3726,7 +3728,13 @@ static struct clk_regmap g12a_mali_0_sel = {
		.ops = &clk_regmap_mux_ops,
		.parent_data = g12a_mali_0_1_parent_data,
		.num_parents = 8,
		.flags = CLK_SET_RATE_NO_REPARENT,
		/*
		* Don't request the parent to change the rate because
		* all GPU frequencies can be derived from the fclk_*
		* clocks and one special GP0_PLL setting. This is
		* important because we need the MPLL clocks for audio.
		*/
		.flags = 0,
		},
		};

		@@ -3743,7 +3751,7 @@ static struct clk_regmap g12a_mali_0_div = {
		&g12a_mali_0_sel.hw
		},
		.num_parents = 1,
		.flags = CLK_SET_RATE_NO_REPARENT,
		.flags = CLK_SET_RATE_PARENT,
		},
		};

		@@ -3759,7 +3767,7 @@ static struct clk_regmap g12a_mali_0 = {
		&g12a_mali_0_div.hw
		},
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT,
		.flags = CLK_SET_RATE_GATE \| CLK_SET_RATE_PARENT,
		},
		};

		@@ -3774,7 +3782,13 @@ static struct clk_regmap g12a_mali_1_sel = {
		.ops = &clk_regmap_mux_ops,
		.parent_data = g12a_mali_0_1_parent_data,
		.num_parents = 8,
		.flags = CLK_SET_RATE_NO_REPARENT,
		/*
		* Don't request the parent to change the rate because
		* all GPU frequencies can be derived from the fclk_*
		* clocks and one special GP0_PLL setting. This is
		* important because we need the MPLL clocks for audio.
		*/
		.flags = 0,
		},
		};

		@@ -3791,7 +3805,7 @@ static struct clk_regmap g12a_mali_1_div = {
		&g12a_mali_1_sel.hw
		},
		.num_parents = 1,
		.flags = CLK_SET_RATE_NO_REPARENT,
		.flags = CLK_SET_RATE_PARENT,
		},
		};

		@@ -3807,7 +3821,7 @@ static struct clk_regmap g12a_mali_1 = {
		&g12a_mali_1_div.hw
		},
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT,
		.flags = CLK_SET_RATE_GATE \| CLK_SET_RATE_PARENT,
		},
		};

		@@ -3827,7 +3841,7 @@ static struct clk_regmap g12a_mali = {
		.ops = &clk_regmap_mux_ops,
		.parent_hws = g12a_mali_parent_hws,
		.num_parents = 2,
		.flags = CLK_SET_RATE_NO_REPARENT,
		.flags = CLK_SET_RATE_PARENT,
		},
		};

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