Commit 6db167df authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'for-linus-2' of git://git.linaro.org/people/rmk/linux-arm 

Pull ARM updates (part two) from Russell King:

 - breakpoint and perf updates from Will Deacon.

 - hypervisor boot mode updates from Will.

 - support for Power State Coordination Interface via the Hypervisor

 - core ARM support for KVM

* 'for-linus-2' of git://git.linaro.org/people/rmk/linux-arm: (32 commits)
  KVM: ARM: Add maintainer entry for KVM/ARM
  KVM: ARM: Power State Coordination Interface implementation
  KVM: ARM: Handle I/O aborts
  KVM: ARM: Handle guest faults in KVM
  KVM: ARM: VFP userspace interface
  KVM: ARM: Demux CCSIDR in the userspace API
  KVM: ARM: User space API for getting/setting co-proc registers
  KVM: ARM: Emulation framework and CP15 emulation
  KVM: ARM: World-switch implementation
  KVM: ARM: Inject IRQs and FIQs from userspace
  KVM: ARM: Memory virtualization setup
  KVM: ARM: Hypervisor initialization
  KVM: ARM: Initial skeleton to compile KVM support
  ARM: Section based HYP idmap
  ARM: Add page table and page defines needed by KVM
  ARM: perf: simplify __hw_perf_event_init err handling
  ARM: perf: remove unnecessary checks for idx < 0
  ARM: perf: handle armpmu_register failing
  ARM: perf: don't pretend to support counting of L1I writes
  ARM: perf: remove redundant NULL check on cpu_pmu
  ...
parents 32f9aab8 9cb54312

Documentation/devicetree/bindings/arm/psci.txt

0 → 100644
+55 −0
Original line number Diff line number Diff line 
* Power State Coordination Interface (PSCI)



Firmware implementing the PSCI functions described in ARM document number

ARM DEN 0022A ("Power State Coordination Interface System Software on ARM

processors") can be used by Linux to initiate various CPU-centric power

operations.



Issue A of the specification describes functions for CPU suspend, hotplug

and migration of secure software.



Functions are invoked by trapping to the privilege level of the PSCI

firmware (specified as part of the binding below) and passing arguments

in a manner similar to that specified by AAPCS:



	 r0		=> 32-bit Function ID / return value

	{r1 - r3}	=> Parameters



Note that the immediate field of the trapping instruction must be set

to #0.





Main node required properties:



 - compatible    : Must be "arm,psci"



 - method        : The method of calling the PSCI firmware. Permitted

                   values are:



                   "smc" : SMC #0, with the register assignments specified

		           in this binding.



                   "hvc" : HVC #0, with the register assignments specified

		           in this binding.



Main node optional properties:



 - cpu_suspend   : Function ID for CPU_SUSPEND operation



 - cpu_off       : Function ID for CPU_OFF operation



 - cpu_on        : Function ID for CPU_ON operation



 - migrate       : Function ID for MIGRATE operation





Example:



	psci {

		compatible	= "arm,psci";

		method		= "smc";

		cpu_suspend	= <0x95c10000>;

		cpu_off		= <0x95c10001>;

		cpu_on		= <0x95c10002>;

		migrate		= <0x95c10003>;

	};

Documentation/virtual/kvm/api.txt

+91 −8
Original line number Diff line number Diff line
@@ -293,7 +293,7 @@ kvm_run' (see below). 
4.11 KVM_GET_REGS



Capability: basic

Architectures: all

Architectures: all except ARM

Type: vcpu ioctl

Parameters: struct kvm_regs (out)

Returns: 0 on success, -1 on error
@@ -314,7 +314,7 @@ struct kvm_regs { 
4.12 KVM_SET_REGS



Capability: basic

Architectures: all

Architectures: all except ARM

Type: vcpu ioctl

Parameters: struct kvm_regs (in)

Returns: 0 on success, -1 on error
@@ -600,7 +600,7 @@ struct kvm_fpu { 
4.24 KVM_CREATE_IRQCHIP



Capability: KVM_CAP_IRQCHIP

Architectures: x86, ia64

Architectures: x86, ia64, ARM

Type: vm ioctl

Parameters: none

Returns: 0 on success, -1 on error
@@ -608,21 +608,39 @@ Returns: 0 on success, -1 on error 
Creates an interrupt controller model in the kernel.  On x86, creates a virtual

ioapic, a virtual PIC (two PICs, nested), and sets up future vcpus to have a

local APIC.  IRQ routing for GSIs 0-15 is set to both PIC and IOAPIC; GSI 16-23

only go to the IOAPIC.  On ia64, a IOSAPIC is created.

only go to the IOAPIC.  On ia64, a IOSAPIC is created. On ARM, a GIC is

created.





4.25 KVM_IRQ_LINE



Capability: KVM_CAP_IRQCHIP

Architectures: x86, ia64

Architectures: x86, ia64, arm

Type: vm ioctl

Parameters: struct kvm_irq_level

Returns: 0 on success, -1 on error



Sets the level of a GSI input to the interrupt controller model in the kernel.

Requires that an interrupt controller model has been previously created with

KVM_CREATE_IRQCHIP.  Note that edge-triggered interrupts require the level

to be set to 1 and then back to 0.

On some architectures it is required that an interrupt controller model has

been previously created with KVM_CREATE_IRQCHIP.  Note that edge-triggered

interrupts require the level to be set to 1 and then back to 0.



ARM can signal an interrupt either at the CPU level, or at the in-kernel irqchip

(GIC), and for in-kernel irqchip can tell the GIC to use PPIs designated for

specific cpus.  The irq field is interpreted like this:



  bits:  | 31 ... 24 | 23  ... 16 | 15    ...    0 |

  field: | irq_type  | vcpu_index |     irq_id     |



The irq_type field has the following values:

- irq_type[0]: out-of-kernel GIC: irq_id 0 is IRQ, irq_id 1 is FIQ

- irq_type[1]: in-kernel GIC: SPI, irq_id between 32 and 1019 (incl.)

               (the vcpu_index field is ignored)

- irq_type[2]: in-kernel GIC: PPI, irq_id between 16 and 31 (incl.)



(The irq_id field thus corresponds nicely to the IRQ ID in the ARM GIC specs)



In both cases, level is used to raise/lower the line.



struct kvm_irq_level {

	union {
@@ -1775,6 +1793,27 @@ registers, find a list below: 
  PPC   | KVM_REG_PPC_VPA_DTL   | 128

  PPC   | KVM_REG_PPC_EPCR	| 32



ARM registers are mapped using the lower 32 bits.  The upper 16 of that

is the register group type, or coprocessor number:



ARM core registers have the following id bit patterns:

  0x4002 0000 0010 <index into the kvm_regs struct:16>



ARM 32-bit CP15 registers have the following id bit patterns:

  0x4002 0000 000F <zero:1> <crn:4> <crm:4> <opc1:4> <opc2:3>



ARM 64-bit CP15 registers have the following id bit patterns:

  0x4003 0000 000F <zero:1> <zero:4> <crm:4> <opc1:4> <zero:3>



ARM CCSIDR registers are demultiplexed by CSSELR value:

  0x4002 0000 0011 00 <csselr:8>



ARM 32-bit VFP control registers have the following id bit patterns:

  0x4002 0000 0012 1 <regno:12>



ARM 64-bit FP registers have the following id bit patterns:

  0x4002 0000 0012 0 <regno:12>



4.69 KVM_GET_ONE_REG



Capability: KVM_CAP_ONE_REG
@@ -2127,6 +2166,50 @@ written, then `n_invalid' invalid entries, invalidating any previously 
valid entries found.





4.77 KVM_ARM_VCPU_INIT



Capability: basic

Architectures: arm

Type: vcpu ioctl

Parameters: struct struct kvm_vcpu_init (in)

Returns: 0 on success; -1 on error

Errors:

  EINVAL:    the target is unknown, or the combination of features is invalid.

  ENOENT:    a features bit specified is unknown.



This tells KVM what type of CPU to present to the guest, and what

optional features it should have.  This will cause a reset of the cpu

registers to their initial values.  If this is not called, KVM_RUN will

return ENOEXEC for that vcpu.



Note that because some registers reflect machine topology, all vcpus

should be created before this ioctl is invoked.



Possible features:

	- KVM_ARM_VCPU_POWER_OFF: Starts the CPU in a power-off state.

	  Depends on KVM_CAP_ARM_PSCI.





4.78 KVM_GET_REG_LIST



Capability: basic

Architectures: arm

Type: vcpu ioctl

Parameters: struct kvm_reg_list (in/out)

Returns: 0 on success; -1 on error

Errors:

  E2BIG:     the reg index list is too big to fit in the array specified by

             the user (the number required will be written into n).



struct kvm_reg_list {

	__u64 n; /* number of registers in reg[] */

	__u64 reg[0];

};



This ioctl returns the guest registers that are supported for the

KVM_GET_ONE_REG/KVM_SET_ONE_REG calls.





5. The kvm_run structure

------------------------

MAINTAINERS

+9 −0
Original line number Diff line number Diff line
@@ -4488,6 +4488,15 @@ F: arch/s390/include/asm/kvm* 
F:	arch/s390/kvm/

F:	drivers/s390/kvm/



KERNEL VIRTUAL MACHINE (KVM) FOR ARM

M:	Christoffer Dall <cdall@cs.columbia.edu>

L:	kvmarm@lists.cs.columbia.edu

W:	http://systems.cs.columbia.edu/projects/kvm-arm

S:	Maintained

F:	arch/arm/include/uapi/asm/kvm*

F:	arch/arm/include/asm/kvm*

F:	arch/arm/kvm/



KEXEC

M:	Eric Biederman <ebiederm@xmission.com>

W:	http://kernel.org/pub/linux/utils/kernel/kexec/

arch/arm/Kconfig

+12 −0
Original line number Diff line number Diff line
@@ -1619,6 +1619,16 @@ config HOTPLUG_CPU 
	  Say Y here to experiment with turning CPUs off and on.  CPUs

	  can be controlled through /sys/devices/system/cpu.



config ARM_PSCI

	bool "Support for the ARM Power State Coordination Interface (PSCI)"

	depends on CPU_V7

	help

	  Say Y here if you want Linux to communicate with system firmware

	  implementing the PSCI specification for CPU-centric power

	  management operations described in ARM document number ARM DEN

	  0022A ("Power State Coordination Interface System Software on

	  ARM processors").



config LOCAL_TIMERS

	bool "Use local timer interrupts"

	depends on SMP
@@ -2324,3 +2334,5 @@ source "security/Kconfig" 
source "crypto/Kconfig"



source "lib/Kconfig"



source "arch/arm/kvm/Kconfig"

arch/arm/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -252,6 +252,7 @@ core-$(CONFIG_FPE_NWFPE) += arch/arm/nwfpe/ 
core-$(CONFIG_FPE_FASTFPE)	+= $(FASTFPE_OBJ)

core-$(CONFIG_VFP)		+= arch/arm/vfp/

core-$(CONFIG_XEN)		+= arch/arm/xen/

core-$(CONFIG_KVM_ARM_HOST) 	+= arch/arm/kvm/



# If we have a machine-specific directory, then include it in the build.

core-y				+= arch/arm/kernel/ arch/arm/mm/ arch/arm/common/

CRA Git | Maintained and supported by SUSTech CRA and CCSE