Commit 6daa9043 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'dmaengine-5.11-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine 

Pull dmaengine updates from Vinod Koul:
 "The last dmaengine updates for this year :)

  This contains couple of new drivers, new device support and updates to
  bunch of drivers.

  New drivers/devices:
   - Qualcomm ADM driver
   - Qualcomm GPI driver
   - Allwinner A100 DMA support
   - Microchip Sama7g5 support
   - Mediatek MT8516 apdma

  Updates:
   - more updates to idxd driver and support for IAX config
   - runtime PM support for dw driver
   - TI drivers"

* tag 'dmaengine-5.11-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine: (75 commits)
  soc: ti: k3-ringacc: Use correct error casting in k3_ringacc_dmarings_init
  dmaengine: ti: k3-udma-glue: Add support for K3 PKTDMA
  dmaengine: ti: k3-udma: Initial support for K3 PKTDMA
  dmaengine: ti: k3-udma: Add support for BCDMA channel TPL handling
  dmaengine: ti: k3-udma: Initial support for K3 BCDMA
  soc: ti: k3-ringacc: add AM64 DMA rings support.
  dmaengine: ti: Add support for k3 event routers
  dmaengine: ti: k3-psil: Add initial map for AM64
  dmaengine: ti: k3-psil: Extend psil_endpoint_config for K3 PKTDMA
  dt-bindings: dma: ti: Add document for K3 PKTDMA
  dt-bindings: dma: ti: Add document for K3 BCDMA
  dmaengine: dmatest: Use dmaengine_get_dma_device
  dmaengine: doc: client: Update for dmaengine_get_dma_device() usage
  dmaengine: Add support for per channel coherency handling
  dmaengine: of-dma: Add support for optional router configuration callback
  dmaengine: ti: k3-udma-glue: Configure the dma_dev for rings
  dmaengine: ti: k3-udma-glue: Get the ringacc from udma_dev
  dmaengine: ti: k3-udma-glue: Add function to get device pointer for DMA API
  dmaengine: ti: k3-udma: Add support for second resource range from sysfw
  dmaengine: ti: k3-udma: Wait for peer teardown completion if supported
  ...
parents 83005cd6 115ff12a

Documentation/ABI/stable/sysfs-driver-dma-idxd

+21 −0
Original line number Diff line number Diff line
@@ -77,6 +77,13 @@ Contact: dmaengine@vger.kernel.org 
Description:    The operation capability bit mask specify the operation types

		supported by the this device.



What:		/sys/bus/dsa/devices/dsa<m>/pasid_enabled

Date:		Oct 27, 2020

KernelVersion:	5.11.0

Contact:	dmaengine@vger.kernel.org

Description:	To indicate if PASID (process address space identifier) is

		enabled or not for this device.



What:           /sys/bus/dsa/devices/dsa<m>/state

Date:           Oct 25, 2019

KernelVersion:  5.6.0
@@ -122,6 +129,13 @@ KernelVersion: 5.10.0 
Contact:	dmaengine@vger.kernel.org

Description:	The last executed device administrative command's status/error.



What:		/sys/bus/dsa/devices/wq<m>.<n>/block_on_fault

Date:		Oct 27, 2020

KernelVersion:	5.11.0

Contact:	dmaengine@vger.kernel.org

Description:	To indicate block on fault is allowed or not for the work queue

		to support on demand paging.



What:           /sys/bus/dsa/devices/wq<m>.<n>/group_id

Date:           Oct 25, 2019

KernelVersion:  5.6.0
@@ -190,6 +204,13 @@ Contact: dmaengine@vger.kernel.org 
Description:	The max batch size for this workqueue. Cannot exceed device

		max batch size. Configurable parameter.



What:		/sys/bus/dsa/devices/wq<m>.<n>/ats_disable

Date:		Nov 13, 2020

KernelVersion:	5.11.0

Contact:	dmaengine@vger.kernel.org

Description:	Indicate whether ATS disable is turned on for the workqueue.

		0 indicates ATS is on, and 1 indicates ATS is off for the workqueue.



What:           /sys/bus/dsa/devices/engine<m>.<n>/group_id

Date:           Oct 25, 2019

KernelVersion:  5.6.0

Documentation/devicetree/bindings/dma/allwinner,sun50i-a64-dma.yaml

+4 −1
Original line number Diff line number Diff line
@@ -21,6 +21,7 @@ properties: 
  compatible:

    oneOf:

      - const: allwinner,sun50i-a64-dma

      - const: allwinner,sun50i-a100-dma

      - const: allwinner,sun50i-h6-dma

      - items:

          - const: allwinner,sun8i-r40-dma
@@ -56,7 +57,9 @@ required: 
if:

  properties:

    compatible:

      const: allwinner,sun50i-h6-dma

      enum:

        - allwinner,sun50i-a100-dma

        - allwinner,sun50i-h6-dma



then:

  properties:

Documentation/devicetree/bindings/dma/atmel-xdma.txt

+2 −1
Original line number Diff line number Diff line
@@ -2,7 +2,8 @@ 


* XDMA Controller

Required properties:

- compatible: Should be "atmel,sama5d4-dma" or "microchip,sam9x60-dma".

- compatible: Should be "atmel,sama5d4-dma", "microchip,sam9x60-dma" or

  "microchip,sama7g5-dma".

- reg: Should contain DMA registers location and length.

- interrupts: Should contain DMA interrupt.

- #dma-cells: Must be <1>, used to represent the number of integer cells in

Documentation/devicetree/bindings/dma/mtk-uart-apdma.txt

+1 −0
Original line number Diff line number Diff line
@@ -4,6 +4,7 @@ Required properties: 
- compatible should contain:

  * "mediatek,mt2712-uart-dma" for MT2712 compatible APDMA

  * "mediatek,mt6577-uart-dma" for MT6577 and all of the above

  * "mediatek,mt8516-uart-dma", "mediatek,mt6577" for MT8516 SoC



- reg: The base address of the APDMA register bank.

Documentation/devicetree/bindings/dma/qcom,gpi.yaml

0 → 100644
+88 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/dma/qcom,gpi.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Qualcomm Technologies Inc GPI DMA controller



maintainers:

  - Vinod Koul <vkoul@kernel.org>



description: |

  QCOM GPI DMA controller provides DMA capabilities for

  peripheral buses such as I2C, UART, and SPI.



allOf:

  - $ref: "dma-controller.yaml#"



properties:

  compatible:

    enum:

      - qcom,sdm845-gpi-dma



  reg:

    maxItems: 1



  interrupts:

    description:

      Interrupt lines for each GPI instance

    maxItems: 13



  "#dma-cells":

    const: 3

    description: >

      DMA clients must use the format described in dma.txt, giving a phandle

      to the DMA controller plus the following 3 integer cells:

      - channel: if set to 0xffffffff, any available channel will be allocated

        for the client. Otherwise, the exact channel specified will be used.

      - seid: serial id of the client as defined in the SoC documentation.

      - client: type of the client as defined in dt-bindings/dma/qcom-gpi.h



  iommus:

    maxItems: 1



  dma-channels:

    maximum: 31



  dma-channel-mask:

    maxItems: 1



required:

  - compatible

  - reg

  - interrupts

  - "#dma-cells"

  - iommus

  - dma-channels

  - dma-channel-mask



additionalProperties: false



examples:

  - |

    #include <dt-bindings/interrupt-controller/arm-gic.h>

    #include <dt-bindings/dma/qcom-gpi.h>

    gpi_dma0: dma-controller@800000 {

        compatible = "qcom,gpi-dma";

        #dma-cells = <3>;

        reg = <0x00800000 0x60000>;

        iommus = <&apps_smmu 0x0016 0x0>;

        dma-channels = <13>;

        dma-channel-mask = <0xfa>;

        interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;

    };



...

CRA Git | Maintained and supported by SUSTech CRA and CCSE