ARM: OMAP5 / DRA7: PM: Enable Mercury retention mode on CPUx powerdomains (6d846c46) · Commits · 戴 / test

In addition to the standard power-management technique, the OMAP5 / DRA7 MPU subsystem also employs an SR3-APG (mercury) power management technology to reduce leakage. It allows for full logic and memories retention on MPU_C0 and MPU_C1 and is controlled by the PRCM_MPU. Only "Fast-mode" is supported on the OMAP5 and DRA7 family of processors. Signed-off-by:

Santosh Shilimkar <santosh.shilimkar@ti.com> [nm@ti.com: minor consolidation] Signed-off-by:

Nishanth Menon <nm@ti.com> Reviewed-by:

Kevin Hilman <khilman@linaro.org> Tested-by:

Kevin Hilman <khilman@linaro.org>

arch/arm/mach-omap2/omap-mpuss-lowpower.c

+16 −0

Original line number	Diff line number	Diff line
		@@ -320,6 +320,21 @@ int omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state)
		}


		/*
		* Enable Mercury Fast HG retention mode by default.
		*/
		static void enable_mercury_retention_mode(void)
		{
		u32 reg;

		reg = omap4_prcm_mpu_read_inst_reg(OMAP54XX_PRCM_MPU_DEVICE_INST,
		OMAP54XX_PRCM_MPU_PRM_PSCON_COUNT_OFFSET);
		/* Enable HG_EN, HG_RAMPUP = fast mode */
		reg \|= BIT(24) \| BIT(25);
		omap4_prcm_mpu_write_inst_reg(reg, OMAP54XX_PRCM_MPU_DEVICE_INST,
		OMAP54XX_PRCM_MPU_PRM_PSCON_COUNT_OFFSET);
		}

		/*
		* Initialise OMAP4 MPUSS
		*/
		@@ -397,6 +412,7 @@ int __init omap4_mpuss_init(void)
		cpu_context_offset = OMAP4_RM_CPU0_CPU0_CONTEXT_OFFSET;
		} else if (soc_is_omap54xx() \|\| soc_is_dra7xx()) {
		cpu_context_offset = OMAP54XX_RM_CPU0_CPU0_CONTEXT_OFFSET;
		enable_mercury_retention_mode();
		}

		return 0;

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