Commit 6d5d346f authored by Ken Chalmers's avatar Ken Chalmers Committed by Alex Deucher
Browse files

drm/amd/display: Eliminate several Maximus-specific code paths 



This allows Maximus emulation to more closely mirror actual silicon
execution.

* Enable pool->base.display_clock creation on Maximus.
* Enable rest of dce110_apply_ctx_to_hw on Maximus.
* Remove apply_ctx_to_hw_fpga (no longer necessary with the full
  dce110_apply_ctx_to_hw enabled).
* Disable the dmcu->funcs->set_psr_wait_loop call in dce112_set_clock
  for Maximus (this was the only fix-up necessary after enabling
  dce110_apply_ctx_to_hw; everything else works unmodified on
  Maximus).

Signed-off-by: default avatarKen Chalmers <ken.chalmers@amd.com>
Reviewed-by: default avatarTony Cheng <Tony.Cheng@amd.com>
Acked-by: default avatarHarry Wentland <harry.wentland@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 73535feb

drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c

+7 −3
Original line number Diff line number Diff line
@@ -34,6 +34,7 @@ 
#include "dcn_calcs.h"

#endif

#include "core_types.h"

#include "dc_types.h"





#define TO_DCE_CLOCKS(clocks)\
@@ -415,9 +416,12 @@ static int dce112_set_clock( 


	bp->funcs->set_dce_clock(bp, &dce_clk_params);



	if (!IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment)) {

		if (clk_dce->dfs_bypass_disp_clk != actual_clock)

			dmcu->funcs->set_psr_wait_loop(dmcu,

					actual_clock / 1000 / 7);

	}



	clk_dce->dfs_bypass_disp_clk = actual_clock;

	return actual_clock;

}

drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

+0 −35
Original line number Diff line number Diff line
@@ -1748,36 +1748,6 @@ static void enable_fbc(struct dc *dc, 
}

#endif



static enum dc_status apply_ctx_to_hw_fpga(

		struct dc *dc,

		struct dc_state *context)

{

	enum dc_status status = DC_ERROR_UNEXPECTED;

	int i;



	for (i = 0; i < MAX_PIPES; i++) {

		struct pipe_ctx *pipe_ctx_old =

				&dc->current_state->res_ctx.pipe_ctx[i];

		struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];



		if (pipe_ctx->stream == NULL)

			continue;



		if (pipe_ctx->stream == pipe_ctx_old->stream)

			continue;



		status = apply_single_controller_ctx_to_hw(

				pipe_ctx,

				context,

				dc);



		if (status != DC_OK)

			return status;

	}



	return DC_OK;

}



static void dce110_reset_hw_ctx_wrap(

		struct dc *dc,

		struct dc_state *context)
@@ -1847,11 +1817,6 @@ enum dc_status dce110_apply_ctx_to_hw( 
	if (context->stream_count <= 0)

		return DC_OK;



	if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {

		apply_ctx_to_hw_fpga(dc, context);

		return DC_OK;

	}



	/* Apply new context */

	dcb->funcs->set_scratch_critical_state(dcb, true);

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c

+5 −7
Original line number Diff line number Diff line
@@ -1316,14 +1316,12 @@ static bool construct( 
		}

	}



	if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {

	pool->base.display_clock = dce120_disp_clk_create(ctx);

	if (pool->base.display_clock == NULL) {

		dm_error("DC: failed to create display clock!\n");

		BREAK_TO_DEBUGGER();

		goto fail;

	}

	}



	pool->base.dmcu = dcn10_dmcu_create(ctx,

			&dmcu_regs,

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