Commit 6d56111c authored by Christoffer Dall's avatar Christoffer Dall
Browse files

KVM: arm/arm64: vgic: Fix GICC_PMR uaccess on GICv3 and clarify ABI 



As an oversight, for GICv2, we accidentally export the GICC_PMR register
in the format of the GICH_VMCR.VMPriMask field in the lower 5 bits of a
word, meaning that userspace must always use the lower 5 bits to
communicate with the KVM device and must shift the value left by 3
places to obtain the actual priority mask level.

Since GICv3 supports the full 8 bits of priority masking in the ICH_VMCR,
we have to fix the value we export when emulating a GICv2 on top of a
hardware GICv3 and exporting the emulated GICv2 state to userspace.

Take the chance to clarify this aspect of the ABI.

Reviewed-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
Signed-off-by: default avatarChristoffer Dall <cdall@linaro.org>
parent 5b0d2cc2

Documentation/virtual/kvm/devices/arm-vgic.txt

+6 −0
Original line number Diff line number Diff line
@@ -83,6 +83,12 @@ Groups: 


    Bits for undefined preemption levels are RAZ/WI.



    For historical reasons and to provide ABI compatibility with userspace we

    export the GICC_PMR register in the format of the GICH_VMCR.VMPriMask

    field in the lower 5 bits of a word, meaning that userspace must always

    use the lower 5 bits to communicate with the KVM device and must shift the

    value left by 3 places to obtain the actual priority mask level.



  Limitations:

    - Priorities are not implemented, and registers are RAZ/WI

    - Currently only implemented for KVM_DEV_TYPE_ARM_VGIC_V2.

include/linux/irqchip/arm-gic.h

+3 −0
Original line number Diff line number Diff line
@@ -96,6 +96,9 @@ 
#define GICH_MISR_EOI			(1 << 0)

#define GICH_MISR_U			(1 << 1)



#define GICV_PMR_PRIORITY_SHIFT		3

#define GICV_PMR_PRIORITY_MASK		(0x1f << GICV_PMR_PRIORITY_SHIFT)



#ifndef __ASSEMBLY__



#include <linux/irqdomain.h>

virt/kvm/arm/vgic/vgic-mmio-v2.c

+18 −2
Original line number Diff line number Diff line
@@ -229,7 +229,15 @@ static unsigned long vgic_mmio_read_vcpuif(struct kvm_vcpu *vcpu, 
		val = vmcr.ctlr;

		break;

	case GIC_CPU_PRIMASK:

		val = vmcr.pmr;

		/*

		 * Our KVM_DEV_TYPE_ARM_VGIC_V2 device ABI exports the

		 * the PMR field as GICH_VMCR.VMPriMask rather than

		 * GICC_PMR.Priority, so we expose the upper five bits of

		 * priority mask to userspace using the lower bits in the

		 * unsigned long.

		 */

		val = (vmcr.pmr & GICV_PMR_PRIORITY_MASK) >>

			GICV_PMR_PRIORITY_SHIFT;

		break;

	case GIC_CPU_BINPOINT:

		val = vmcr.bpr;
@@ -262,7 +270,15 @@ static void vgic_mmio_write_vcpuif(struct kvm_vcpu *vcpu, 
		vmcr.ctlr = val;

		break;

	case GIC_CPU_PRIMASK:

		vmcr.pmr = val;

		/*

		 * Our KVM_DEV_TYPE_ARM_VGIC_V2 device ABI exports the

		 * the PMR field as GICH_VMCR.VMPriMask rather than

		 * GICC_PMR.Priority, so we expose the upper five bits of

		 * priority mask to userspace using the lower bits in the

		 * unsigned long.

		 */

		vmcr.pmr = (val << GICV_PMR_PRIORITY_SHIFT) &

			GICV_PMR_PRIORITY_MASK;

		break;

	case GIC_CPU_BINPOINT:

		vmcr.bpr = val;

virt/kvm/arm/vgic/vgic-v2.c

+4 −4
Original line number Diff line number Diff line
@@ -206,8 +206,8 @@ void vgic_v2_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcrp) 
		GICH_VMCR_ALIAS_BINPOINT_MASK;

	vmcr |= (vmcrp->bpr << GICH_VMCR_BINPOINT_SHIFT) &

		GICH_VMCR_BINPOINT_MASK;

	vmcr |= (vmcrp->pmr << GICH_VMCR_PRIMASK_SHIFT) &

		GICH_VMCR_PRIMASK_MASK;

	vmcr |= ((vmcrp->pmr >> GICV_PMR_PRIORITY_SHIFT) <<

		 GICH_VMCR_PRIMASK_SHIFT) & GICH_VMCR_PRIMASK_MASK;



	vcpu->arch.vgic_cpu.vgic_v2.vgic_vmcr = vmcr;

}
@@ -222,8 +222,8 @@ void vgic_v2_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcrp) 
			GICH_VMCR_ALIAS_BINPOINT_SHIFT;

	vmcrp->bpr  = (vmcr & GICH_VMCR_BINPOINT_MASK) >>

			GICH_VMCR_BINPOINT_SHIFT;

	vmcrp->pmr  = (vmcr & GICH_VMCR_PRIMASK_MASK) >>

			GICH_VMCR_PRIMASK_SHIFT;

	vmcrp->pmr  = ((vmcr & GICH_VMCR_PRIMASK_MASK) >>

			GICH_VMCR_PRIMASK_SHIFT) << GICV_PMR_PRIORITY_SHIFT;

}



void vgic_v2_enable(struct kvm_vcpu *vcpu)

virt/kvm/arm/vgic/vgic.h

+8 −1
Original line number Diff line number Diff line
@@ -81,11 +81,18 @@ static inline bool irq_is_pending(struct vgic_irq *irq) 
		return irq->pending_latch || irq->line_level;

}



/*

 * This struct provides an intermediate representation of the fields contained

 * in the GICH_VMCR and ICH_VMCR registers, such that code exporting the GIC

 * state to userspace can generate either GICv2 or GICv3 CPU interface

 * registers regardless of the hardware backed GIC used.

 */

struct vgic_vmcr {

	u32	ctlr;

	u32	abpr;

	u32	bpr;

	u32	pmr;

	u32	pmr;  /* Priority mask field in the GICC_PMR and

		       * ICC_PMR_EL1 priority field format */

	/* Below member variable are valid only for GICv3 */

	u32	grpen0;

	u32	grpen1;

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