Commit 6d25ef77 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'drm-fixes-2020-01-10' of git://anongit.freedesktop.org/drm/drm 

Pull drm fixes from Dave Airlie:
 "Pre-LCA pull request I'm not sure how things will look next week,
  myself and Daniel are at LCA and I'm speaking quite late, so if I get
  my talk finished I'll probably process fixes.

  This week has a bunch of i915 fixes, some amdgpu fixes, one sun4i, one
  core MST, and one core fb_helper fix. More details below:

  core:
   - mst Fix NO_STOP_BIT bit offset (Wayne)

  fb_helper:
   - fb_helper: Fix bits_per_pixel param set behavior to round up
     (Geert)

  sun4i:
   - Fix RGB_DIV clock min divider on old hardware (Chen-Yu)

  amdgpu:
   - Stability fix for raven
   - Reduce pixel encoding to if max clock is exceeded on HDMI to allow
     additional high res modes
   - enable DRIVER_SYNCOBJ_TIMELINE for amdgpu

  i915:
   - Fix GitLab issue #446 causing GPU hangs: Do not restore invalid RS
     state
   - Fix GitLab issue #846: Restore coarse power gating that was
     disabled by initial RC66 context corruption security fixes.
   - Revert f6ec9483 ("drm/i915: extend audio CDCLK>=2*BCLK
     constraint to more platforms") to avoid screen flicker
   - Fix to fill in unitialized uabi_instance in virtual engine uAPI
   - Add two missing W/As for ICL and EHL"

* tag 'drm-fixes-2020-01-10' of git://anongit.freedesktop.org/drm/drm:
  drm/amdgpu: add DRIVER_SYNCOBJ_TIMELINE to amdgpu
  drm/amd/display: Reduce HDMI pixel encoding if max clock is exceeded
  Revert "drm/amdgpu: Set no-retry as default."
  drm/fb-helper: Round up bits_per_pixel if possible
  drm/sun4i: tcon: Set RGB DCLK min. divider based on hardware model
  drm/i915/dp: Disable Port sync mode correctly on teardown
  drm/i915: Add Wa_1407352427:icl,ehl
  drm/i915: Add Wa_1408615072 and Wa_1407596294 to icl,ehl
  drm/i915/gt: Restore coarse power gating
  drm/i915/gt: Do not restore invalid RS state
  drm/i915: Limit audio CDCLK>=2*BCLK constraint back to GLK only
  drm/i915/gt: Mark up virtual engine uabi_instance
  drm/dp_mst: correct the shifting in DP_REMOTE_I2C_READ
parents 5e7c1b75 023b3b0e

drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c

+4 −3
Original line number Diff line number Diff line
@@ -142,7 +142,7 @@ int amdgpu_async_gfx_ring = 1; 
int amdgpu_mcbp = 0;

int amdgpu_discovery = -1;

int amdgpu_mes = 0;

int amdgpu_noretry = 1;

int amdgpu_noretry;

int amdgpu_force_asic_type = -1;



struct amdgpu_mgpu_info mgpu_info = {
@@ -588,7 +588,7 @@ MODULE_PARM_DESC(mes, 
module_param_named(mes, amdgpu_mes, int, 0444);



MODULE_PARM_DESC(noretry,

	"Disable retry faults (0 = retry enabled, 1 = retry disabled (default))");

	"Disable retry faults (0 = retry enabled (default), 1 = retry disabled)");

module_param_named(noretry, amdgpu_noretry, int, 0644);



/**
@@ -1359,7 +1359,8 @@ static struct drm_driver kms_driver = { 
	.driver_features =

	    DRIVER_USE_AGP | DRIVER_ATOMIC |

	    DRIVER_GEM |

	    DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ,

	    DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ |

	    DRIVER_SYNCOBJ_TIMELINE,

	.load = amdgpu_driver_load_kms,

	.open = amdgpu_driver_open_kms,

	.postclose = amdgpu_driver_postclose_kms,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

+23 −22
Original line number Diff line number Diff line
@@ -3356,27 +3356,21 @@ get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing) 
	return color_space;

}



static void reduce_mode_colour_depth(struct dc_crtc_timing *timing_out)

{

	if (timing_out->display_color_depth <= COLOR_DEPTH_888)

		return;



	timing_out->display_color_depth--;

}



static void adjust_colour_depth_from_display_info(struct dc_crtc_timing *timing_out,

static bool adjust_colour_depth_from_display_info(

	struct dc_crtc_timing *timing_out,

	const struct drm_display_info *info)

{

	enum dc_color_depth depth = timing_out->display_color_depth;

	int normalized_clk;

	if (timing_out->display_color_depth <= COLOR_DEPTH_888)

		return;

	do {

		normalized_clk = timing_out->pix_clk_100hz / 10;

		/* YCbCr 4:2:0 requires additional adjustment of 1/2 */

		if (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420)

			normalized_clk /= 2;

		/* Adjusting pix clock following on HDMI spec based on colour depth */

		switch (timing_out->display_color_depth) {

		switch (depth) {

		case COLOR_DEPTH_888:

			break;

		case COLOR_DEPTH_101010:

			normalized_clk = (normalized_clk * 30) / 24;

			break;
@@ -3387,14 +3381,15 @@ static void adjust_colour_depth_from_display_info(struct dc_crtc_timing *timing_ 
			normalized_clk = (normalized_clk * 48) / 24;

			break;

		default:

			return;

			/* The above depths are the only ones valid for HDMI. */

			return false;

		}

		if (normalized_clk <= info->max_tmds_clock)

			return;

		reduce_mode_colour_depth(timing_out);



	} while (timing_out->display_color_depth > COLOR_DEPTH_888);



		if (normalized_clk <= info->max_tmds_clock) {

			timing_out->display_color_depth = depth;

			return true;

		}

	} while (--depth > COLOR_DEPTH_666);

	return false;

}



static void fill_stream_properties_from_drm_display_mode(
@@ -3474,9 +3469,15 @@ static void fill_stream_properties_from_drm_display_mode( 


	stream->out_transfer_func->type = TF_TYPE_PREDEFINED;

	stream->out_transfer_func->tf = TRANSFER_FUNCTION_SRGB;

	if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)

	if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) {

		if (!adjust_colour_depth_from_display_info(timing_out, info) &&

		    drm_mode_is_420_also(info, mode_in) &&

		    timing_out->pixel_encoding != PIXEL_ENCODING_YCBCR420) {

			timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;

			adjust_colour_depth_from_display_info(timing_out, info);

		}

	}

}



static void fill_audio_info(struct audio_info *audio_info,

			    const struct drm_connector *drm_connector,

drivers/gpu/drm/drm_dp_mst_topology.c

+1 −1
Original line number Diff line number Diff line
@@ -393,7 +393,7 @@ drm_dp_encode_sideband_req(const struct drm_dp_sideband_msg_req_body *req, 
			memcpy(&buf[idx], req->u.i2c_read.transactions[i].bytes, req->u.i2c_read.transactions[i].num_bytes);

			idx += req->u.i2c_read.transactions[i].num_bytes;



			buf[idx] = (req->u.i2c_read.transactions[i].no_stop_bit & 0x1) << 5;

			buf[idx] = (req->u.i2c_read.transactions[i].no_stop_bit & 0x1) << 4;

			buf[idx] |= (req->u.i2c_read.transactions[i].i2c_transaction_delay & 0xf);

			idx++;

		}

drivers/gpu/drm/drm_fb_helper.c

+6 −1
Original line number Diff line number Diff line
@@ -1283,7 +1283,7 @@ int drm_fb_helper_check_var(struct fb_var_screeninfo *var, 
	 * Changes struct fb_var_screeninfo are currently not pushed back

	 * to KMS, hence fail if different settings are requested.

	 */

	if (var->bits_per_pixel != fb->format->cpp[0] * 8 ||

	if (var->bits_per_pixel > fb->format->cpp[0] * 8 ||

	    var->xres > fb->width || var->yres > fb->height ||

	    var->xres_virtual > fb->width || var->yres_virtual > fb->height) {

		DRM_DEBUG("fb requested width/height/bpp can't fit in current fb "
@@ -1308,6 +1308,11 @@ int drm_fb_helper_check_var(struct fb_var_screeninfo *var, 
		drm_fb_helper_fill_pixel_fmt(var, fb->format->depth);

	}



	/*

	 * Likewise, bits_per_pixel should be rounded up to a supported value.

	 */

	var->bits_per_pixel = fb->format->cpp[0] * 8;



	/*

	 * drm fbdev emulation doesn't support changing the pixel format at all,

	 * so reject all pixel format changing requests.

drivers/gpu/drm/i915/display/intel_audio.c

+2 −2
Original line number Diff line number Diff line
@@ -856,7 +856,7 @@ static unsigned long i915_audio_component_get_power(struct device *kdev) 
		}



		/* Force CDCLK to 2*BCLK as long as we need audio powered. */

		if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))

		if (IS_GEMINILAKE(dev_priv))

			glk_force_audio_cdclk(dev_priv, true);



		if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
@@ -875,7 +875,7 @@ static void i915_audio_component_put_power(struct device *kdev, 


	/* Stop forcing CDCLK to 2*BCLK if no need for audio to be powered. */

	if (--dev_priv->audio_power_refcount == 0)

		if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))

		if (IS_GEMINILAKE(dev_priv))

			glk_force_audio_cdclk(dev_priv, false);



	intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO, cookie);

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