Commit 6d10c395 authored by Peter Ujfalusi's avatar Peter Ujfalusi Committed by Sekhar Nori
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ARM: edma: Get IP configuration from HW (number of channels, tc, etc) 



From CCCFG register of eDMA3 we can get all the needed information for the
driver about the IP:
Number of channels: NUM_DMACH
Number of regions: NUM_REGN
Number of slots (PaRAM sets): NUM_PAENTRY
Number of TC/EQ: NUM_EVQUE

In case when booted with DT or the queue_priority_mapping is not provided
set up a default priority map.

Signed-off-by: default avatarPeter Ujfalusi <peter.ujfalusi@ti.com>
Acked-by: default avatarJoel Fernandes <joelf@ti.com>
Signed-off-by: default avatarSekhar Nori <nsekhar@ti.com>
parent 643efcff

arch/arm/common/edma.c

+73 −42
Original line number Diff line number Diff line
@@ -102,6 +102,12 @@ 
#define PARM_OFFSET(param_no)	(EDMA_PARM + ((param_no) << 5))



#define EDMA_DCHMAP	0x0100  /* 64 registers */



/* CCCFG register */

#define GET_NUM_DMACH(x)	(x & 0x7) /* bits 0-2 */

#define GET_NUM_PAENTRY(x)	((x & 0x7000) >> 12) /* bits 12-14 */

#define GET_NUM_EVQUE(x)	((x & 0x70000) >> 16) /* bits 16-18 */

#define GET_NUM_REGN(x)		((x & 0x300000) >> 20) /* bits 20-21 */

#define CHMAP_EXIST		BIT(24)



#define EDMA_MAX_DMACH           64
@@ -1408,6 +1414,67 @@ void edma_clear_event(unsigned channel) 
}

EXPORT_SYMBOL(edma_clear_event);



static int edma_setup_from_hw(struct device *dev, struct edma_soc_info *pdata,

			      struct edma *edma_cc)

{

	int i;

	u32 value, cccfg;

	s8 (*queue_priority_map)[2];



	/* Decode the eDMA3 configuration from CCCFG register */

	cccfg = edma_read(0, EDMA_CCCFG);



	value = GET_NUM_REGN(cccfg);

	edma_cc->num_region = BIT(value);



	value = GET_NUM_DMACH(cccfg);

	edma_cc->num_channels = BIT(value + 1);



	value = GET_NUM_PAENTRY(cccfg);

	edma_cc->num_slots = BIT(value + 4);



	value = GET_NUM_EVQUE(cccfg);

	edma_cc->num_tc = value + 1;



	dev_dbg(dev, "eDMA3 HW configuration (cccfg: 0x%08x):\n", cccfg);

	dev_dbg(dev, "num_region: %u\n", edma_cc->num_region);

	dev_dbg(dev, "num_channel: %u\n", edma_cc->num_channels);

	dev_dbg(dev, "num_slot: %u\n", edma_cc->num_slots);

	dev_dbg(dev, "num_tc: %u\n", edma_cc->num_tc);



	/* Nothing need to be done if queue priority is provided */

	if (pdata->queue_priority_mapping)

		return 0;



	/*

	 * Configure TC/queue priority as follows:

	 * Q0 - priority 0

	 * Q1 - priority 1

	 * Q2 - priority 2

	 * ...

	 * The meaning of priority numbers: 0 highest priority, 7 lowest

	 * priority. So Q0 is the highest priority queue and the last queue has

	 * the lowest priority.

	 */

	queue_priority_map = devm_kzalloc(dev,

					  (edma_cc->num_tc + 1) * sizeof(s8),

					  GFP_KERNEL);

	if (!queue_priority_map)

		return -ENOMEM;



	for (i = 0; i < edma_cc->num_tc; i++) {

		queue_priority_map[i][0] = i;

		queue_priority_map[i][1] = i;

	}

	queue_priority_map[i][0] = -1;

	queue_priority_map[i][1] = -1;



	pdata->queue_priority_mapping = queue_priority_map;

	pdata->default_queue = 0;



	return 0;

}



#if IS_ENABLED(CONFIG_OF) && IS_ENABLED(CONFIG_DMADEVICES)



static int edma_of_read_u32_to_s16_array(const struct device_node *np,
@@ -1476,50 +1543,16 @@ static int edma_of_parse_dt(struct device *dev, 
			    struct device_node *node,

			    struct edma_soc_info *pdata)

{

	int ret = 0, i;

	u32 value;

	int ret = 0;

	struct property *prop;

	size_t sz;

	struct edma_rsv_info *rsv_info;

	s8 (*queue_priority_map)[2];



	ret = of_property_read_u32(node, "dma-channels", &value);

	if (ret < 0)

		return ret;

	pdata->n_channel = value;



	ret = of_property_read_u32(node, "ti,edma-regions", &value);

	if (ret < 0)

		return ret;

	pdata->n_region = value;



	ret = of_property_read_u32(node, "ti,edma-slots", &value);

	if (ret < 0)

		return ret;

	pdata->n_slot = value;



	pdata->n_tc = 3;



	rsv_info = devm_kzalloc(dev, sizeof(struct edma_rsv_info), GFP_KERNEL);

	if (!rsv_info)

		return -ENOMEM;

	pdata->rsv = rsv_info;



	queue_priority_map = devm_kzalloc(dev, 8*sizeof(s8), GFP_KERNEL);

	if (!queue_priority_map)

		return -ENOMEM;



	for (i = 0; i < 3; i++) {

		queue_priority_map[i][0] = i;

		queue_priority_map[i][1] = i;

	}

	queue_priority_map[i][0] = -1;

	queue_priority_map[i][1] = -1;



	pdata->queue_priority_mapping = queue_priority_map;



	pdata->default_queue = 0;



	prop = of_find_property(node, "ti,edma-xbar-event-map", &sz);

	if (prop)

		ret = edma_xbar_event_map(dev, node, pdata, sz);
@@ -1639,14 +1672,12 @@ static int edma_probe(struct platform_device *pdev) 
		if (!edma_cc[j])

			return -ENOMEM;



		edma_cc[j]->num_channels = min_t(unsigned, info[j]->n_channel,

							EDMA_MAX_DMACH);

		edma_cc[j]->num_slots = min_t(unsigned, info[j]->n_slot,

							EDMA_MAX_PARAMENTRY);

		edma_cc[j]->num_tc = info[j]->n_tc;

		/* Get eDMA3 configuration from IP */

		ret = edma_setup_from_hw(dev, info[j], edma_cc[j]);

		if (ret)

			return ret;



		edma_cc[j]->default_queue = info[j]->default_queue;

		edma_cc[j]->num_region = info[j]->n_region;



		dev_dbg(&pdev->dev, "DMA REG BASE ADDR=%p\n",

			edmacc_regs_base[j]);

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