Commit 6d0ef316 authored by Pu Wen's avatar Pu Wen Committed by Borislav Petkov
Browse files

x86/events: Add Hygon Dhyana support to PMU infrastructure 



The PMU architecture for the Hygon Dhyana CPU is similar to the AMD
Family 17h one. To support it, call amd_pmu_init() to share the AMD PMU
initialization flow, and change the PMU name to "HYGON".

The Hygon Dhyana CPU supports both legacy and extension PMC MSRs (perf
counter registers and event selection registers), so add Hygon Dhyana
support in the similar way as AMD does.

Signed-off-by: default avatarPu Wen <puwen@hygon.cn>
Signed-off-by: default avatarBorislav Petkov <bp@suse.de>
Reviewed-by: default avatarBorislav Petkov <bp@suse.de>
Cc: tglx@linutronix.de
Cc: mingo@redhat.com
Cc: hpa@zytor.com
Cc: x86@kernel.org
Cc: thomas.lendacky@amd.com
Link: https://lkml.kernel.org/r/9d93ed54a975f33ef7247e0967960f4ce5d3d990.1537533369.git.puwen@hygon.cn
parent 0b13bec7

arch/x86/events/amd/core.c

+4 −0
Original line number Diff line number Diff line
@@ -669,6 +669,10 @@ static int __init amd_core_pmu_init(void) 
		 * We fallback to using default amd_get_event_constraints.

		 */

		break;

	case 0x18:

		pr_cont("Fam18h ");

		/* Using default amd_get_event_constraints. */

		break;

	default:

		pr_err("core perfctr but no constraints; unknown hardware!\n");

		return -ENODEV;

arch/x86/events/amd/uncore.c

+13 −7
Original line number Diff line number Diff line
@@ -507,17 +507,19 @@ static int __init amd_uncore_init(void) 
{

	int ret = -ENODEV;



	if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD)

	if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD &&

	    boot_cpu_data.x86_vendor != X86_VENDOR_HYGON)

		return -ENODEV;



	if (!boot_cpu_has(X86_FEATURE_TOPOEXT))

		return -ENODEV;



	if (boot_cpu_data.x86 == 0x17) {

	if (boot_cpu_data.x86 == 0x17 || boot_cpu_data.x86 == 0x18) {

		/*

		 * For F17h, the Northbridge counters are repurposed as Data

		 * Fabric counters. Also, L3 counters are supported too. The PMUs

		 * are exported based on  family as either L2 or L3 and NB or DF.

		 * For F17h or F18h, the Northbridge counters are

		 * repurposed as Data Fabric counters. Also, L3

		 * counters are supported too. The PMUs are exported

		 * based on family as either L2 or L3 and NB or DF.

		 */

		num_counters_nb		  = NUM_COUNTERS_NB;

		num_counters_llc	  = NUM_COUNTERS_L3;
@@ -547,7 +549,9 @@ static int __init amd_uncore_init(void) 
		if (ret)

			goto fail_nb;



		pr_info("AMD NB counters detected\n");

		pr_info("%s NB counters detected\n",

			boot_cpu_data.x86_vendor == X86_VENDOR_HYGON ?

				"HYGON" : "AMD");

		ret = 0;

	}
@@ -561,7 +565,9 @@ static int __init amd_uncore_init(void) 
		if (ret)

			goto fail_llc;



		pr_info("AMD LLC counters detected\n");

		pr_info("%s LLC counters detected\n",

			boot_cpu_data.x86_vendor == X86_VENDOR_HYGON ?

				"HYGON" : "AMD");

		ret = 0;

	}

arch/x86/events/core.c

+4 −0
Original line number Diff line number Diff line
@@ -1776,6 +1776,10 @@ static int __init init_hw_perf_events(void) 
	case X86_VENDOR_AMD:

		err = amd_pmu_init();

		break;

	case X86_VENDOR_HYGON:

		err = amd_pmu_init();

		x86_pmu.name = "HYGON";

		break;

	default:

		err = -ENOTSUPP;

	}

arch/x86/kernel/cpu/perfctr-watchdog.c

+2 −0
Original line number Diff line number Diff line
@@ -46,6 +46,7 @@ static inline unsigned int nmi_perfctr_msr_to_bit(unsigned int msr) 
{

	/* returns the bit offset of the performance counter register */

	switch (boot_cpu_data.x86_vendor) {

	case X86_VENDOR_HYGON:

	case X86_VENDOR_AMD:

		if (msr >= MSR_F15H_PERF_CTR)

			return (msr - MSR_F15H_PERF_CTR) >> 1;
@@ -74,6 +75,7 @@ static inline unsigned int nmi_evntsel_msr_to_bit(unsigned int msr) 
{

	/* returns the bit offset of the event selection register */

	switch (boot_cpu_data.x86_vendor) {

	case X86_VENDOR_HYGON:

	case X86_VENDOR_AMD:

		if (msr >= MSR_F15H_PERF_CTL)

			return (msr - MSR_F15H_PERF_CTL) >> 1;

CRA Git | Maintained and supported by SUSTech CRA and CCSE