Commit 6cecf916 authored by Stephen Warren's avatar Stephen Warren
Browse files

ARM: tegra: convert device tree files to use IRQ defines 



Use the GIC and standard IRQ binding defines in all IRQ specifiers.

Signed-off-by: default avatarStephen Warren <swarren@nvidia.com>
parent 3325f1bc

arch/arm/boot/dts/tegra114-dalmore.dts

+1 −1
Original line number Diff line number Diff line
@@ -748,7 +748,7 @@ 
			compatible = "ti,tps65090";

			reg = <0x48>;

			interrupt-parent = <&gpio>;

			interrupts = <72 0x04>; /* gpio PJ0 */

			interrupts = <TEGRA_GPIO(J, 0) IRQ_TYPE_LEVEL_HIGH>;



			vsys1-supply = <&vdd_ac_bat_reg>;

			vsys2-supply = <&vdd_ac_bat_reg>;

arch/arm/boot/dts/tegra114.dtsi

+79 −72
Original line number Diff line number Diff line 
#include <dt-bindings/gpio/tegra-gpio.h>

#include <dt-bindings/interrupt-controller/arm-gic.h>



#include "skeleton.dtsi"
@@ -21,18 +22,19 @@ 
		      <0x50042000 0x1000>,

		      <0x50044000 0x2000>,

		      <0x50046000 0x2000>;

		interrupts = <1 9 0xf04>;

		interrupts = <GIC_PPI 9

			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;

	};



	timer@60005000 {

		compatible = "nvidia,tegra114-timer", "nvidia,tegra20-timer";

		reg = <0x60005000 0x400>;

		interrupts = <0 0 0x04

			      0 1 0x04

			      0 41 0x04

			      0 42 0x04

			      0 121 0x04

			      0 122 0x04>;

		interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&tegra_car 5>;

	};
@@ -45,38 +47,38 @@ 
	apbdma: dma {

		compatible = "nvidia,tegra114-apbdma";

		reg = <0x6000a000 0x1400>;

		interrupts = <0 104 0x04

			      0 105 0x04

			      0 106 0x04

			      0 107 0x04

			      0 108 0x04

			      0 109 0x04

			      0 110 0x04

			      0 111 0x04

			      0 112 0x04

			      0 113 0x04

			      0 114 0x04

			      0 115 0x04

			      0 116 0x04

			      0 117 0x04

			      0 118 0x04

			      0 119 0x04

			      0 128 0x04

			      0 129 0x04

			      0 130 0x04

			      0 131 0x04

			      0 132 0x04

			      0 133 0x04

			      0 134 0x04

			      0 135 0x04

			      0 136 0x04

			      0 137 0x04

			      0 138 0x04

			      0 139 0x04

			      0 140 0x04

			      0 141 0x04

			      0 142 0x04

			      0 143 0x04>;

		interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&tegra_car 34>;

	};
@@ -88,14 +90,14 @@ 
	gpio: gpio {

		compatible = "nvidia,tegra114-gpio", "nvidia,tegra30-gpio";

		reg = <0x6000d000 0x1000>;

		interrupts = <0 32 0x04

			      0 33 0x04

			      0 34 0x04

			      0 35 0x04

			      0 55 0x04

			      0 87 0x04

			      0 89 0x04

			      0 125 0x04>;

		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;

		#gpio-cells = <2>;

		gpio-controller;

		#interrupt-cells = <2>;
@@ -120,7 +122,7 @@ 
		compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";

		reg = <0x70006000 0x40>;

		reg-shift = <2>;

		interrupts = <0 36 0x04>;

		interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;

		nvidia,dma-request-selector = <&apbdma 8>;

		status = "disabled";

		clocks = <&tegra_car 6>;
@@ -130,7 +132,7 @@ 
		compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";

		reg = <0x70006040 0x40>;

		reg-shift = <2>;

		interrupts = <0 37 0x04>;

		interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;

		nvidia,dma-request-selector = <&apbdma 9>;

		status = "disabled";

		clocks = <&tegra_car 192>;
@@ -140,7 +142,7 @@ 
		compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";

		reg = <0x70006200 0x100>;

		reg-shift = <2>;

		interrupts = <0 46 0x04>;

		interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;

		nvidia,dma-request-selector = <&apbdma 10>;

		status = "disabled";

		clocks = <&tegra_car 55>;
@@ -150,7 +152,7 @@ 
		compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";

		reg = <0x70006300 0x100>;

		reg-shift = <2>;

		interrupts = <0 90 0x04>;

		interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;

		nvidia,dma-request-selector = <&apbdma 19>;

		status = "disabled";

		clocks = <&tegra_car 65>;
@@ -167,7 +169,7 @@ 
	i2c@7000c000 {

		compatible = "nvidia,tegra114-i2c";

		reg = <0x7000c000 0x100>;

		interrupts = <0 38 0x04>;

		interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;

		#address-cells = <1>;

		#size-cells = <0>;

		clocks = <&tegra_car 12>;
@@ -178,7 +180,7 @@ 
	i2c@7000c400 {

		compatible = "nvidia,tegra114-i2c";

		reg = <0x7000c400 0x100>;

		interrupts = <0 84 0x04>;

		interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;

		#address-cells = <1>;

		#size-cells = <0>;

		clocks = <&tegra_car 54>;
@@ -189,7 +191,7 @@ 
	i2c@7000c500 {

		compatible = "nvidia,tegra114-i2c";

		reg = <0x7000c500 0x100>;

		interrupts = <0 92 0x04>;

		interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;

		#address-cells = <1>;

		#size-cells = <0>;

		clocks = <&tegra_car 67>;
@@ -200,7 +202,7 @@ 
	i2c@7000c700 {

		compatible = "nvidia,tegra114-i2c";

		reg = <0x7000c700 0x100>;

		interrupts = <0 120 0x04>;

		interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;

		#address-cells = <1>;

		#size-cells = <0>;

		clocks = <&tegra_car 103>;
@@ -211,7 +213,7 @@ 
	i2c@7000d000 {

		compatible = "nvidia,tegra114-i2c";

		reg = <0x7000d000 0x100>;

		interrupts = <0 53 0x04>;

		interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;

		#address-cells = <1>;

		#size-cells = <0>;

		clocks = <&tegra_car 47>;
@@ -222,7 +224,7 @@ 
	spi@7000d400 {

		compatible = "nvidia,tegra114-spi";

		reg = <0x7000d400 0x200>;

		interrupts = <0 59 0x04>;

		interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;

		nvidia,dma-request-selector = <&apbdma 15>;

		#address-cells = <1>;

		#size-cells = <0>;
@@ -234,7 +236,7 @@ 
	spi@7000d600 {

		compatible = "nvidia,tegra114-spi";

		reg = <0x7000d600 0x200>;

		interrupts = <0 82 0x04>;

		interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;

		nvidia,dma-request-selector = <&apbdma 16>;

		#address-cells = <1>;

		#size-cells = <0>;
@@ -246,7 +248,7 @@ 
	spi@7000d800 {

		compatible = "nvidia,tegra114-spi";

		reg = <0x7000d800 0x200>;

		interrupts = <0 83 0x04>;

		interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;

		nvidia,dma-request-selector = <&apbdma 17>;

		#address-cells = <1>;

		#size-cells = <0>;
@@ -258,7 +260,7 @@ 
	spi@7000da00 {

		compatible = "nvidia,tegra114-spi";

		reg = <0x7000da00 0x200>;

		interrupts = <0 93 0x04>;

		interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;

		nvidia,dma-request-selector = <&apbdma 18>;

		#address-cells = <1>;

		#size-cells = <0>;
@@ -270,7 +272,7 @@ 
	spi@7000dc00 {

		compatible = "nvidia,tegra114-spi";

		reg = <0x7000dc00 0x200>;

		interrupts = <0 94 0x04>;

		interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;

		nvidia,dma-request-selector = <&apbdma 27>;

		#address-cells = <1>;

		#size-cells = <0>;
@@ -282,7 +284,7 @@ 
	spi@7000de00 {

		compatible = "nvidia,tegra114-spi";

		reg = <0x7000de00 0x200>;

		interrupts = <0 79 0x04>;

		interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;

		nvidia,dma-request-selector = <&apbdma 28>;

		#address-cells = <1>;

		#size-cells = <0>;
@@ -294,14 +296,14 @@ 
	rtc {

		compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc";

		reg = <0x7000e000 0x100>;

		interrupts = <0 2 0x04>;

		interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&tegra_car 4>;

	};



	kbc {

		compatible = "nvidia,tegra114-kbc";

		reg = <0x7000e200 0x100>;

		interrupts = <0 85 0x04>;

		interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&tegra_car 36>;

		status = "disabled";

	};
@@ -327,7 +329,7 @@ 
	sdhci@78000000 {

		compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";

		reg = <0x78000000 0x200>;

		interrupts = <0 14 0x04>;

		interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&tegra_car 14>;

		status = "disable";

	};
@@ -335,7 +337,7 @@ 
	sdhci@78000200 {

		compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";

		reg = <0x78000200 0x200>;

		interrupts = <0 15 0x04>;

		interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&tegra_car 9>;

		status = "disable";

	};
@@ -343,7 +345,7 @@ 
	sdhci@78000400 {

		compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";

		reg = <0x78000400 0x200>;

		interrupts = <0 19 0x04>;

		interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&tegra_car 69>;

		status = "disable";

	};
@@ -351,7 +353,7 @@ 
	sdhci@78000600 {

		compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";

		reg = <0x78000600 0x200>;

		interrupts = <0 31 0x04>;

		interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&tegra_car 15>;

		status = "disable";

	};
@@ -387,9 +389,14 @@ 


	timer {

		compatible = "arm,armv7-timer";

		interrupts = <1 13 0xf08>,

			     <1 14 0xf08>,

			     <1 11 0xf08>,

			     <1 10 0xf08>;

		interrupts =

			<GIC_PPI 13

				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,

			<GIC_PPI 14

				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,

			<GIC_PPI 11

				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,

			<GIC_PPI 10

				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;

	};

};

arch/arm/boot/dts/tegra20-colibri-512.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -218,7 +218,7 @@ 
		pmic: tps6586x@34 {

			compatible = "ti,tps6586x";

			reg = <0x34>;

			interrupts = <0 86 0x4>;

			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;



			ti,system-power-controller;

arch/arm/boot/dts/tegra20-harmony.dts

+2 −2
Original line number Diff line number Diff line
@@ -263,7 +263,7 @@ 
			compatible = "wlf,wm8903";

			reg = <0x1a>;

			interrupt-parent = <&gpio>;

			interrupts = <TEGRA_GPIO(X, 3) 0x04>;

			interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>;



			gpio-controller;

			#gpio-cells = <2>;
@@ -291,7 +291,7 @@ 
		pmic: tps6586x@34 {

			compatible = "ti,tps6586x";

			reg = <0x34>;

			interrupts = <0 86 0x4>;

			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;



			ti,system-power-controller;

arch/arm/boot/dts/tegra20-medcom-wide.dts

+1 −1
Original line number Diff line number Diff line
@@ -15,7 +15,7 @@ 
			compatible = "wlf,wm8903";

			reg = <0x1a>;

			interrupt-parent = <&gpio>;

			interrupts = <TEGRA_GPIO(X, 3) 0x04>;

			interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>;



			gpio-controller;

			#gpio-cells = <2>;

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