Commit 6ce5bfe9 authored Jun 28, 2019 by Lionel Landwerlin Committed by Jani Nikula Jul 29, 2019

drm/i915: whitelist PS_(DEPTH|INVOCATION)_COUNT



CFL:C0+ changed the status of those registers which are now
blacklisted by default.

This is breaking a number of CTS tests on GL & Vulkan :

  KHR-GL45.pipeline_statistics_query_tests_ARB.functional_fragment_shader_invocations (GL)

  dEQP-VK.query_pool.statistics_query.fragment_shader_invocations.* (Vulkan)

v2: Only use one whitelist entry (Lionel)

Bspec: 14091
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: stable@vger.kernel.org # 6883eab27481: drm/i915: Support flags in whitlist WAs
Cc: stable@vger.kernel.org
Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20190628120720.21682-3-lionel.g.landwerlin@intel.com


(cherry picked from commit 2c903da5)
Signed-off-by: Jani Nikula <jani.nikula@intel.com>

parent c270cac4

drivers/gpu/drm/i915/gt/intel_workarounds.c

+16 −1

Original line number	Diff line number	Diff line
		@@ -1098,10 +1098,25 @@ static void glk_whitelist_build(struct intel_engine_cs *engine)

		static void cfl_whitelist_build(struct intel_engine_cs *engine)
		{
		struct i915_wa_list *w = &engine->whitelist;

		if (engine->class != RENDER_CLASS)
		return;

		gen9_whitelist_build(&engine->whitelist);
		gen9_whitelist_build(w);

		/*
		* WaAllowPMDepthAndInvocationCountAccessFromUMD:cfl,whl,cml,aml
		*
		* This covers 4 register which are next to one another :
		* - PS_INVOCATION_COUNT
		* - PS_INVOCATION_COUNT_UDW
		* - PS_DEPTH_COUNT
		* - PS_DEPTH_COUNT_UDW
		*/
		whitelist_reg_ext(w, PS_INVOCATION_COUNT,
		RING_FORCE_TO_NONPRIV_RD \|
		RING_FORCE_TO_NONPRIV_RANGE_4);
		}

		static void cnl_whitelist_build(struct intel_engine_cs *engine)

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