Commit 6cd21d79 authored by David S. Miller's avatar David S. Miller
Browse files

Merge tag 'wireless-drivers-next-for-davem-2016-02-12' of... 

Merge tag 'wireless-drivers-next-for-davem-2016-02-12' of git://git.kernel.org/pub/scm/linux/kernel/git/kvalo/wireless-drivers-next



Kalle Valo says:

====================
Major changes:

wl12xx

* add device tree support for SPI

mwifiex

* add debugfs file to read chip information
* add MSIx support for newer pcie chipsets (8997 onwards)
* add schedule scan support
* add WoWLAN net-detect support
* firmware dump support for w8997 chipset

iwlwifi

* continue the work on multiple Rx queues
* add support for beacon storing used in low power states
* use the regular firmware image of WoWLAN
* fix 8000 devices for Big Endian machines
* more firmware debug hooks
* add support for P2P Client snoozing
* make the beacon filtering for AP mode configurable
* fix transmit queues overflow with LSO

libertas

* add support for setting power save via cfg80211
====================

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents 27090cbd 11e70824

Documentation/devicetree/bindings/net/wireless/ti,wlcore,spi.txt

0 → 100644
+36 −0
Original line number Diff line number Diff line 
* Texas Instruments wl1271 wireless lan controller



The wl1271 chip can be connected via SPI or via SDIO. This

document describes the binding for the SPI connected chip.



Required properties:

- compatible :          Should be "ti,wl1271"

- reg :                 Chip select address of device

- spi-max-frequency :   Maximum SPI clocking speed of device in Hz

- ref-clock-frequency : Reference clock frequency

- interrupt-parent, interrupts :

                        Should contain parameters for 1 interrupt line.

                        Interrupt parameters: parent, line number, type.

- vwlan-supply :        Point the node of the regulator that powers/enable the wl1271 chip



Optional properties:

- clock-xtal :          boolean, clock is generated from XTAL



- Please consult Documentation/devicetree/bindings/spi/spi-bus.txt

  for optional SPI connection related properties,



Examples:



&spi1 {

	wl1271@1 {

		compatible = "ti,wl1271";



		reg = <1>;

		spi-max-frequency = <48000000>;

		clock-xtal;

		ref-clock-frequency = <38400000>;

		interrupt-parent = <&gpio3>;

		interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;

		vwlan-supply = <&vwlan_fixed>;

	};

};

drivers/bcma/bcma_private.h

+0 −1
Original line number Diff line number Diff line
@@ -48,7 +48,6 @@ void bcma_core_chipcommon_early_init(struct bcma_drv_cc *cc); 
void bcma_core_chipcommon_init(struct bcma_drv_cc *cc);

void bcma_chipco_bcm4331_ext_pa_lines_ctl(struct bcma_drv_cc *cc, bool enable);

#ifdef CONFIG_BCMA_DRIVER_MIPS

void bcma_chipco_serial_init(struct bcma_drv_cc *cc);

extern struct platform_device bcma_pflash_dev;

#endif /* CONFIG_BCMA_DRIVER_MIPS */

drivers/bcma/driver_chipcommon.c

+12 −4
Original line number Diff line number Diff line
@@ -15,6 +15,8 @@ 
#include <linux/platform_device.h>

#include <linux/bcma/bcma.h>



static void bcma_chipco_serial_init(struct bcma_drv_cc *cc);



static inline u32 bcma_cc_write32_masked(struct bcma_drv_cc *cc, u16 offset,

					 u32 mask, u32 value)

{
@@ -115,6 +117,8 @@ int bcma_chipco_watchdog_register(struct bcma_drv_cc *cc) 


void bcma_core_chipcommon_early_init(struct bcma_drv_cc *cc)

{

	struct bcma_bus *bus = cc->core->bus;



	if (cc->early_setup_done)

		return;
@@ -129,6 +133,9 @@ void bcma_core_chipcommon_early_init(struct bcma_drv_cc *cc) 
	if (cc->capabilities & BCMA_CC_CAP_PMU)

		bcma_pmu_early_init(cc);



	if (IS_BUILTIN(CONFIG_BCM47XX) && bus->hosttype == BCMA_HOSTTYPE_SOC)

		bcma_chipco_serial_init(cc);



	cc->early_setup_done = true;

}
@@ -185,11 +192,12 @@ u32 bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks) 
			ticks = 2;

		else if (ticks > maxt)

			ticks = maxt;

		bcma_cc_write32(cc, BCMA_CC_PMU_WATCHDOG, ticks);

		bcma_pmu_write32(cc, BCMA_CC_PMU_WATCHDOG, ticks);

	} else {

		struct bcma_bus *bus = cc->core->bus;



		if (bus->chipinfo.id != BCMA_CHIP_ID_BCM4707 &&

		    bus->chipinfo.id != BCMA_CHIP_ID_BCM47094 &&

		    bus->chipinfo.id != BCMA_CHIP_ID_BCM53018)

			bcma_core_set_clockmode(cc->core,

						ticks ? BCMA_CLKMODE_FAST : BCMA_CLKMODE_DYNAMIC);
@@ -314,9 +322,9 @@ u32 bcma_chipco_gpio_pulldown(struct bcma_drv_cc *cc, u32 mask, u32 value) 
	return res;

}



#ifdef CONFIG_BCMA_DRIVER_MIPS

void bcma_chipco_serial_init(struct bcma_drv_cc *cc)

static void bcma_chipco_serial_init(struct bcma_drv_cc *cc)

{

#if IS_BUILTIN(CONFIG_BCM47XX)

	unsigned int irq;

	u32 baud_base;

	u32 i;
@@ -358,5 +366,5 @@ void bcma_chipco_serial_init(struct bcma_drv_cc *cc) 
		ports[i].baud_base = baud_base;

		ports[i].reg_shift = 0;

	}

#endif /* CONFIG_BCM47XX */

}
 
#endif /* CONFIG_BCMA_DRIVER_MIPS */

drivers/bcma/driver_chipcommon_pmu.c

+52 −42
Original line number Diff line number Diff line
@@ -15,44 +15,44 @@ 


u32 bcma_chipco_pll_read(struct bcma_drv_cc *cc, u32 offset)

{

	bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset);

	bcma_cc_read32(cc, BCMA_CC_PLLCTL_ADDR);

	return bcma_cc_read32(cc, BCMA_CC_PLLCTL_DATA);

	bcma_pmu_write32(cc, BCMA_CC_PMU_PLLCTL_ADDR, offset);

	bcma_pmu_read32(cc, BCMA_CC_PMU_PLLCTL_ADDR);

	return bcma_pmu_read32(cc, BCMA_CC_PMU_PLLCTL_DATA);

}

EXPORT_SYMBOL_GPL(bcma_chipco_pll_read);



void bcma_chipco_pll_write(struct bcma_drv_cc *cc, u32 offset, u32 value)

{

	bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset);

	bcma_cc_read32(cc, BCMA_CC_PLLCTL_ADDR);

	bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, value);

	bcma_pmu_write32(cc, BCMA_CC_PMU_PLLCTL_ADDR, offset);

	bcma_pmu_read32(cc, BCMA_CC_PMU_PLLCTL_ADDR);

	bcma_pmu_write32(cc, BCMA_CC_PMU_PLLCTL_DATA, value);

}

EXPORT_SYMBOL_GPL(bcma_chipco_pll_write);



void bcma_chipco_pll_maskset(struct bcma_drv_cc *cc, u32 offset, u32 mask,

			     u32 set)

{

	bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset);

	bcma_cc_read32(cc, BCMA_CC_PLLCTL_ADDR);

	bcma_cc_maskset32(cc, BCMA_CC_PLLCTL_DATA, mask, set);

	bcma_pmu_write32(cc, BCMA_CC_PMU_PLLCTL_ADDR, offset);

	bcma_pmu_read32(cc, BCMA_CC_PMU_PLLCTL_ADDR);

	bcma_pmu_maskset32(cc, BCMA_CC_PMU_PLLCTL_DATA, mask, set);

}

EXPORT_SYMBOL_GPL(bcma_chipco_pll_maskset);



void bcma_chipco_chipctl_maskset(struct bcma_drv_cc *cc,

				 u32 offset, u32 mask, u32 set)

{

	bcma_cc_write32(cc, BCMA_CC_CHIPCTL_ADDR, offset);

	bcma_cc_read32(cc, BCMA_CC_CHIPCTL_ADDR);

	bcma_cc_maskset32(cc, BCMA_CC_CHIPCTL_DATA, mask, set);

	bcma_pmu_write32(cc, BCMA_CC_PMU_CHIPCTL_ADDR, offset);

	bcma_pmu_read32(cc, BCMA_CC_PMU_CHIPCTL_ADDR);

	bcma_pmu_maskset32(cc, BCMA_CC_PMU_CHIPCTL_DATA, mask, set);

}

EXPORT_SYMBOL_GPL(bcma_chipco_chipctl_maskset);



void bcma_chipco_regctl_maskset(struct bcma_drv_cc *cc, u32 offset, u32 mask,

				u32 set)

{

	bcma_cc_write32(cc, BCMA_CC_REGCTL_ADDR, offset);

	bcma_cc_read32(cc, BCMA_CC_REGCTL_ADDR);

	bcma_cc_maskset32(cc, BCMA_CC_REGCTL_DATA, mask, set);

	bcma_pmu_write32(cc, BCMA_CC_PMU_REGCTL_ADDR, offset);

	bcma_pmu_read32(cc, BCMA_CC_PMU_REGCTL_ADDR);

	bcma_pmu_maskset32(cc, BCMA_CC_PMU_REGCTL_DATA, mask, set);

}

EXPORT_SYMBOL_GPL(bcma_chipco_regctl_maskset);
@@ -60,18 +60,18 @@ static u32 bcma_pmu_xtalfreq(struct bcma_drv_cc *cc) 
{

	u32 ilp_ctl, alp_hz;



	if (!(bcma_cc_read32(cc, BCMA_CC_PMU_STAT) &

	if (!(bcma_pmu_read32(cc, BCMA_CC_PMU_STAT) &

	      BCMA_CC_PMU_STAT_EXT_LPO_AVAIL))

		return 0;



	bcma_cc_write32(cc, BCMA_CC_PMU_XTAL_FREQ,

	bcma_pmu_write32(cc, BCMA_CC_PMU_XTAL_FREQ,

			 BIT(BCMA_CC_PMU_XTAL_FREQ_MEASURE_SHIFT));

	usleep_range(1000, 2000);



	ilp_ctl = bcma_cc_read32(cc, BCMA_CC_PMU_XTAL_FREQ);

	ilp_ctl = bcma_pmu_read32(cc, BCMA_CC_PMU_XTAL_FREQ);

	ilp_ctl &= BCMA_CC_PMU_XTAL_FREQ_ILPCTL_MASK;



	bcma_cc_write32(cc, BCMA_CC_PMU_XTAL_FREQ, 0);

	bcma_pmu_write32(cc, BCMA_CC_PMU_XTAL_FREQ, 0);



	alp_hz = ilp_ctl * 32768 / 4;

	return (alp_hz + 50000) / 100000 * 100;
@@ -127,8 +127,8 @@ static void bcma_pmu2_pll_init0(struct bcma_drv_cc *cc, u32 xtalfreq) 
		mask = (u32)~(BCMA_RES_4314_HT_AVAIL |

			      BCMA_RES_4314_MACPHY_CLK_AVAIL);



		bcma_cc_mask32(cc, BCMA_CC_PMU_MINRES_MSK, mask);

		bcma_cc_mask32(cc, BCMA_CC_PMU_MAXRES_MSK, mask);

		bcma_pmu_mask32(cc, BCMA_CC_PMU_MINRES_MSK, mask);

		bcma_pmu_mask32(cc, BCMA_CC_PMU_MAXRES_MSK, mask);

		bcma_wait_value(cc->core, BCMA_CLKCTLST,

				BCMA_CLKCTLST_HAVEHT, 0, 20000);

		break;
@@ -140,7 +140,7 @@ static void bcma_pmu2_pll_init0(struct bcma_drv_cc *cc, u32 xtalfreq) 


	/* Flush */

	if (cc->pmu.rev >= 2)

		bcma_cc_set32(cc, BCMA_CC_PMU_CTL, BCMA_CC_PMU_CTL_PLL_UPD);

		bcma_pmu_set32(cc, BCMA_CC_PMU_CTL, BCMA_CC_PMU_CTL_PLL_UPD);



	/* TODO: Do we need to update OTP? */

}
@@ -195,9 +195,9 @@ static void bcma_pmu_resources_init(struct bcma_drv_cc *cc) 


	/* Set the resource masks. */

	if (min_msk)

		bcma_cc_write32(cc, BCMA_CC_PMU_MINRES_MSK, min_msk);

		bcma_pmu_write32(cc, BCMA_CC_PMU_MINRES_MSK, min_msk);

	if (max_msk)

		bcma_cc_write32(cc, BCMA_CC_PMU_MAXRES_MSK, max_msk);

		bcma_pmu_write32(cc, BCMA_CC_PMU_MAXRES_MSK, max_msk);



	/*

	 * Add some delay; allow resources to come up and settle.
@@ -269,22 +269,32 @@ static void bcma_pmu_workarounds(struct bcma_drv_cc *cc) 


void bcma_pmu_early_init(struct bcma_drv_cc *cc)

{

	struct bcma_bus *bus = cc->core->bus;

	u32 pmucap;



	pmucap = bcma_cc_read32(cc, BCMA_CC_PMU_CAP);

	if (cc->core->id.rev >= 35 &&

	    cc->capabilities_ext & BCMA_CC_CAP_EXT_AOB_PRESENT) {

		cc->pmu.core = bcma_find_core(bus, BCMA_CORE_PMU);

		if (!cc->pmu.core)

			bcma_warn(bus, "Couldn't find expected PMU core");

	}

	if (!cc->pmu.core)

		cc->pmu.core = cc->core;



	pmucap = bcma_pmu_read32(cc, BCMA_CC_PMU_CAP);

	cc->pmu.rev = (pmucap & BCMA_CC_PMU_CAP_REVISION);



	bcma_debug(cc->core->bus, "Found rev %u PMU (capabilities 0x%08X)\n",

		   cc->pmu.rev, pmucap);

	bcma_debug(bus, "Found rev %u PMU (capabilities 0x%08X)\n", cc->pmu.rev,

		   pmucap);

}



void bcma_pmu_init(struct bcma_drv_cc *cc)

{

	if (cc->pmu.rev == 1)

		bcma_cc_mask32(cc, BCMA_CC_PMU_CTL,

		bcma_pmu_mask32(cc, BCMA_CC_PMU_CTL,

				~BCMA_CC_PMU_CTL_NOILPONW);

	else

		bcma_cc_set32(cc, BCMA_CC_PMU_CTL,

		bcma_pmu_set32(cc, BCMA_CC_PMU_CTL,

			       BCMA_CC_PMU_CTL_NOILPONW);



	bcma_pmu_pll_init(cc);
@@ -472,8 +482,8 @@ u32 bcma_pmu_get_cpu_clock(struct bcma_drv_cc *cc) 
static void bcma_pmu_spuravoid_pll_write(struct bcma_drv_cc *cc, u32 offset,

					 u32 value)

{

	bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset);

	bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, value);

	bcma_pmu_write32(cc, BCMA_CC_PMU_PLLCTL_ADDR, offset);

	bcma_pmu_write32(cc, BCMA_CC_PMU_PLLCTL_DATA, value);

}



void bcma_pmu_spuravoid_pllupdate(struct bcma_drv_cc *cc, int spuravoid)
@@ -497,20 +507,20 @@ void bcma_pmu_spuravoid_pllupdate(struct bcma_drv_cc *cc, int spuravoid) 
		       bus->chipinfo.id == BCMA_CHIP_ID_BCM53572) ? 6 : 0;



		/* RMW only the P1 divider */

		bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR,

		bcma_pmu_write32(cc, BCMA_CC_PMU_PLLCTL_ADDR,

				BCMA_CC_PMU_PLL_CTL0 + phypll_offset);

		tmp = bcma_cc_read32(cc, BCMA_CC_PLLCTL_DATA);

		tmp = bcma_pmu_read32(cc, BCMA_CC_PMU_PLLCTL_DATA);

		tmp &= (~(BCMA_CC_PMU1_PLL0_PC0_P1DIV_MASK));

		tmp |= (bcm5357_bcm43236_p1div[spuravoid] << BCMA_CC_PMU1_PLL0_PC0_P1DIV_SHIFT);

		bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, tmp);

		bcma_pmu_write32(cc, BCMA_CC_PMU_PLLCTL_DATA, tmp);



		/* RMW only the int feedback divider */

		bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR,

		bcma_pmu_write32(cc, BCMA_CC_PMU_PLLCTL_ADDR,

				BCMA_CC_PMU_PLL_CTL2 + phypll_offset);

		tmp = bcma_cc_read32(cc, BCMA_CC_PLLCTL_DATA);

		tmp = bcma_pmu_read32(cc, BCMA_CC_PMU_PLLCTL_DATA);

		tmp &= ~(BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_MASK);

		tmp |= (bcm5357_bcm43236_ndiv[spuravoid]) << BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_SHIFT;

		bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, tmp);

		bcma_pmu_write32(cc, BCMA_CC_PMU_PLLCTL_DATA, tmp);



		tmp = BCMA_CC_PMU_CTL_PLL_UPD;

		break;
@@ -646,7 +656,7 @@ void bcma_pmu_spuravoid_pllupdate(struct bcma_drv_cc *cc, int spuravoid) 
		break;

	}



	tmp |= bcma_cc_read32(cc, BCMA_CC_PMU_CTL);

	bcma_cc_write32(cc, BCMA_CC_PMU_CTL, tmp);

	tmp |= bcma_pmu_read32(cc, BCMA_CC_PMU_CTL);

	bcma_pmu_write32(cc, BCMA_CC_PMU_CTL, tmp);

}

EXPORT_SYMBOL_GPL(bcma_pmu_spuravoid_pllupdate);

drivers/bcma/driver_chipcommon_sflash.c

+1 −0
Original line number Diff line number Diff line
@@ -38,6 +38,7 @@ static const struct bcma_sflash_tbl_e bcma_sflash_st_tbl[] = { 
	{ "M25P32", 0x15, 0x10000, 64, },

	{ "M25P64", 0x16, 0x10000, 128, },

	{ "M25FL128", 0x17, 0x10000, 256, },

	{ "MX25L25635F", 0x18, 0x10000, 512, },

	{ NULL },

};

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