Commit 6c90b86a authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'mmc-v5.6-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc 

Pull MMC fixes from Ulf Hansson:

 - rtsx_pci: Fix support for some various speed modes

 - sdhci-of-at91: Fix support for GPIO card detect on SAMA5D2

 - sdhci-cadence: Fix support for DDR52 speed mode for eMMC on UniPhier

 - sdhci-acpi: Fix broken WP support on Acer Aspire Switch 10

 - sdhci-acpi: Workaround FW bug for suspend on Lenovo Miix 320

* tag 'mmc-v5.6-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc:
  mmc: rtsx_pci: Fix support for speed-modes that relies on tuning
  mmc: sdhci-of-at91: fix cd-gpios for SAMA5D2
  mmc: sdhci-cadence: set SDHCI_QUIRK2_PRESET_VALUE_BROKEN for UniPhier
  mmc: sdhci-acpi: Disable write protect detection on Acer Aspire Switch 10 (SW5-012)
  mmc: sdhci-acpi: Switch signal voltage back to 3.3V on suspend on external microSD on Lenovo Miix 320
parents cd607737 4686392c

drivers/misc/cardreader/rts5227.c

+1 −1
Original line number Diff line number Diff line
@@ -394,7 +394,7 @@ static const struct pcr_ops rts522a_pcr_ops = { 
void rts522a_init_params(struct rtsx_pcr *pcr)

{

	rts5227_init_params(pcr);



	pcr->tx_initial_phase = SET_CLOCK_PHASE(20, 20, 11);

	pcr->reg_pm_ctrl3 = RTS522A_PM_CTRL3;



	pcr->option.ocp_en = 1;

drivers/misc/cardreader/rts5249.c

+2 −0
Original line number Diff line number Diff line
@@ -618,6 +618,7 @@ static const struct pcr_ops rts524a_pcr_ops = { 
void rts524a_init_params(struct rtsx_pcr *pcr)

{

	rts5249_init_params(pcr);

	pcr->tx_initial_phase = SET_CLOCK_PHASE(27, 29, 11);

	pcr->option.ltr_l1off_sspwrgate = LTR_L1OFF_SSPWRGATE_5250_DEF;

	pcr->option.ltr_l1off_snooze_sspwrgate =

		LTR_L1OFF_SNOOZE_SSPWRGATE_5250_DEF;
@@ -733,6 +734,7 @@ static const struct pcr_ops rts525a_pcr_ops = { 
void rts525a_init_params(struct rtsx_pcr *pcr)

{

	rts5249_init_params(pcr);

	pcr->tx_initial_phase = SET_CLOCK_PHASE(25, 29, 11);

	pcr->option.ltr_l1off_sspwrgate = LTR_L1OFF_SSPWRGATE_5250_DEF;

	pcr->option.ltr_l1off_snooze_sspwrgate =

		LTR_L1OFF_SNOOZE_SSPWRGATE_5250_DEF;

drivers/misc/cardreader/rts5260.c

+1 −1
Original line number Diff line number Diff line
@@ -662,7 +662,7 @@ void rts5260_init_params(struct rtsx_pcr *pcr) 
	pcr->sd30_drive_sel_1v8 = CFG_DRIVER_TYPE_B;

	pcr->sd30_drive_sel_3v3 = CFG_DRIVER_TYPE_B;

	pcr->aspm_en = ASPM_L1_EN;

	pcr->tx_initial_phase = SET_CLOCK_PHASE(1, 29, 16);

	pcr->tx_initial_phase = SET_CLOCK_PHASE(27, 29, 11);

	pcr->rx_initial_phase = SET_CLOCK_PHASE(24, 6, 5);



	pcr->ic_version = rts5260_get_ic_version(pcr);

drivers/misc/cardreader/rts5261.c

+1 −1
Original line number Diff line number Diff line
@@ -764,7 +764,7 @@ void rts5261_init_params(struct rtsx_pcr *pcr) 
	pcr->sd30_drive_sel_1v8 = CFG_DRIVER_TYPE_B;

	pcr->sd30_drive_sel_3v3 = CFG_DRIVER_TYPE_B;

	pcr->aspm_en = ASPM_L1_EN;

	pcr->tx_initial_phase = SET_CLOCK_PHASE(20, 27, 16);

	pcr->tx_initial_phase = SET_CLOCK_PHASE(27, 27, 11);

	pcr->rx_initial_phase = SET_CLOCK_PHASE(24, 6, 5);



	pcr->ic_version = rts5261_get_ic_version(pcr);

drivers/mmc/host/rtsx_pci_sdmmc.c

+8 −5
Original line number Diff line number Diff line
@@ -606,19 +606,22 @@ static int sd_change_phase(struct realtek_pci_sdmmc *host, 
		u8 sample_point, bool rx)

{

	struct rtsx_pcr *pcr = host->pcr;



	u16 SD_VP_CTL = 0;

	dev_dbg(sdmmc_dev(host), "%s(%s): sample_point = %d\n",

			__func__, rx ? "RX" : "TX", sample_point);



	rtsx_pci_write_register(pcr, CLK_CTL, CHANGE_CLK, CHANGE_CLK);

	if (rx)

	if (rx) {

		SD_VP_CTL = SD_VPRX_CTL;

		rtsx_pci_write_register(pcr, SD_VPRX_CTL,

			PHASE_SELECT_MASK, sample_point);

	else

	} else {

		SD_VP_CTL = SD_VPTX_CTL;

		rtsx_pci_write_register(pcr, SD_VPTX_CTL,

			PHASE_SELECT_MASK, sample_point);

	rtsx_pci_write_register(pcr, SD_VPCLK0_CTL, PHASE_NOT_RESET, 0);

	rtsx_pci_write_register(pcr, SD_VPCLK0_CTL, PHASE_NOT_RESET,

	}

	rtsx_pci_write_register(pcr, SD_VP_CTL, PHASE_NOT_RESET, 0);

	rtsx_pci_write_register(pcr, SD_VP_CTL, PHASE_NOT_RESET,

				PHASE_NOT_RESET);

	rtsx_pci_write_register(pcr, CLK_CTL, CHANGE_CLK, 0);

	rtsx_pci_write_register(pcr, SD_CFG1, SD_ASYNC_FIFO_NOT_RST, 0);

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