Commit 6c66350d authored Oct 12, 2017 by mike.travis@hpe.com Committed by Thomas Gleixner Oct 16, 2017

x86/tsc: Provide a means to disable TSC ART



On systems where multiple chassis are reset asynchronously, and thus
the TSC counters are started asynchronously, the offset needed to
convert to TSC to ART would be different.  Disable ART in that case
and rely on the TSC counters to supply the accurate time.

Signed-off-by: Mike Travis <mike.travis@hpe.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Cc: Prarit Bhargava <prarit@redhat.com>
Cc: Dimitri Sivanich <dimitri.sivanich@hpe.com>
Cc: Russ Anderson <russ.anderson@hpe.com>
Cc: Andrew Banman <andrew.banman@hpe.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Bin Gao <bin.gao@linux.intel.com>
Link: https://lkml.kernel.org/r/20171012163202.289397994@stormcage.americas.sgi.com

parent 41e7864a

arch/x86/kernel/tsc.c

+6 −2

Original line number	Diff line number	Diff line
		@@ -962,10 +962,14 @@ static void detect_art(void)
		if (boot_cpu_data.cpuid_level < ART_CPUID_LEAF)
		return;

		/* Don't enable ART in a VM, non-stop TSC and TSC_ADJUST required */
		/*
		* Don't enable ART in a VM, non-stop TSC and TSC_ADJUST required,
		* and the TSC counter resets must not occur asynchronously.
		*/
		if (boot_cpu_has(X86_FEATURE_HYPERVISOR) \|\|
		!boot_cpu_has(X86_FEATURE_NONSTOP_TSC) \|\|
		!boot_cpu_has(X86_FEATURE_TSC_ADJUST))
		!boot_cpu_has(X86_FEATURE_TSC_ADJUST) \|\|
		tsc_async_resets)
		return;

		cpuid(ART_CPUID_LEAF, &art_to_tsc_denominator,

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