Commit 6c61403a authored by Linus Torvalds's avatar Linus Torvalds
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Merge branch 'for-linus' of git://git.infradead.org/users/vkoul/slave-dma 

Pull slave-dmaengine updates from Vinod Koul:
 - New driver for Qcom bam dma
 - New driver for RCAR peri-peri
 - New driver for FSL eDMA
 - Various odd fixes and updates thru the subsystem

* 'for-linus' of git://git.infradead.org/users/vkoul/slave-dma: (29 commits)
  dmaengine: add Qualcomm BAM dma driver
  shdma: add R-Car Audio DMAC peri peri driver
  dmaengine: sirf: enable generic dt binding for dma channels
  dma: omap-dma: Implement device_slave_caps callback
  dmaengine: qcom_bam_dma: Add device tree binding
  dma: dw: Add suspend and resume handling for PCI mode DW_DMAC.
  dma: dw: allocate memory in two stages in probe
  Add new line to test result strings produced in verbose mode
  dmaengine: pch_dma: use tasklet_kill in teardown
  dmaengine: at_hdmac: use tasklet_kill in teardown
  dma: cppi41: start tear down only if channel is busy
  usb: musb: musb_cppi41: Dont reprogram DMA if tear down is initiated
  dmaengine: s3c24xx-dma: make phy->irq signed for error handling
  dma: imx-dma: Add missing module owner field
  dma: imx-dma: Replace printk with dev_*
  dma: fsl-edma: fix static checker warning of NULL dereference
  dma: Remove comment about embedding dma_slave_config into custom structs
  dma: mmp_tdma: move to generic device tree binding
  dma: mmp_pdma: add IRQF_SHARED when request irq
  dma: edma: Fix memory leak in edma_prep_dma_cyclic()
  ...
parents edf2377c 8673bcef

Documentation/devicetree/bindings/dma/fsl-edma.txt

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* Freescale enhanced Direct Memory Access(eDMA) Controller



  The eDMA channels have multiplex capability by programmble memory-mapped

registers. channels are split into two groups, called DMAMUX0 and DMAMUX1,

specific DMA request source can only be multiplexed by any channel of certain

group, DMAMUX0 or DMAMUX1, but not both.



* eDMA Controller

Required properties:

- compatible :

	- "fsl,vf610-edma" for eDMA used similar to that on Vybrid vf610 SoC

- reg : Specifies base physical address(s) and size of the eDMA registers.

	The 1st region is eDMA control register's address and size.

	The 2nd and the 3rd regions are programmable channel multiplexing

	control register's address and size.

- interrupts : A list of interrupt-specifiers, one for each entry in

	interrupt-names.

- interrupt-names : Should contain:

	"edma-tx" - the transmission interrupt

	"edma-err" - the error interrupt

- #dma-cells : Must be <2>.

	The 1st cell specifies the DMAMUX(0 for DMAMUX0 and 1 for DMAMUX1).

	Specific request source can only be multiplexed by specific channels

	group called DMAMUX.

	The 2nd cell specifies the request source(slot) ID.

	See the SoC's reference manual for all the supported request sources.

- dma-channels : Number of channels supported by the controller

- clock-names : A list of channel group clock names. Should contain:

	"dmamux0" - clock name of mux0 group

	"dmamux1" - clock name of mux1 group

- clocks : A list of phandle and clock-specifier pairs, one for each entry in

	clock-names.



Optional properties:

- big-endian: If present registers and hardware scatter/gather descriptors

	of the eDMA are implemented in big endian mode, otherwise in little

	mode.





Examples:



edma0: dma-controller@40018000 {

	#dma-cells = <2>;

	compatible = "fsl,vf610-edma";

	reg = <0x40018000 0x2000>,

		<0x40024000 0x1000>,

		<0x40025000 0x1000>;

	interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>,

		<0 9 IRQ_TYPE_LEVEL_HIGH>;

	interrupt-names = "edma-tx", "edma-err";

	dma-channels = <32>;

	clock-names = "dmamux0", "dmamux1";

	clocks = <&clks VF610_CLK_DMAMUX0>,

		<&clks VF610_CLK_DMAMUX1>;

};





* DMA clients

DMA client drivers that uses the DMA function must use the format described

in the dma.txt file, using a two-cell specifier for each channel: the 1st

specifies the channel group(DMAMUX) in which this request can be multiplexed,

and the 2nd specifies the request source.



Examples:



sai2: sai@40031000 {

	compatible = "fsl,vf610-sai";

	reg = <0x40031000 0x1000>;

	interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;

	clock-names = "sai";

	clocks = <&clks VF610_CLK_SAI2>;

	dma-names = "tx", "rx";

	dmas = <&edma0 0 21>,

		<&edma0 0 20>;

	status = "disabled";

};

Documentation/devicetree/bindings/dma/qcom_bam_dma.txt

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QCOM BAM DMA controller



Required properties:

- compatible: must contain "qcom,bam-v1.4.0" for MSM8974

- reg: Address range for DMA registers

- interrupts: Should contain the one interrupt shared by all channels

- #dma-cells: must be <1>, the cell in the dmas property of the client device

  represents the channel number

- clocks: required clock

- clock-names: must contain "bam_clk" entry

- qcom,ee : indicates the active Execution Environment identifier (0-7) used in

  the secure world.



Example:



	uart-bam: dma@f9984000 = {

		compatible = "qcom,bam-v1.4.0";

		reg = <0xf9984000 0x15000>;

		interrupts = <0 94 0>;

		clocks = <&gcc GCC_BAM_DMA_AHB_CLK>;

		clock-names = "bam_clk";

		#dma-cells = <1>;

		qcom,ee = <0>;

	};



DMA clients must use the format described in the dma.txt file, using a two cell

specifier for each channel.



Example:

	serial@f991e000 {

		compatible = "qcom,msm-uart";

		reg = <0xf991e000 0x1000>

			<0xf9944000 0x19000>;

		interrupts = <0 108 0>;

		clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,

			<&gcc GCC_BLSP1_AHB_CLK>;

		clock-names = "core", "iface";



		dmas = <&uart-bam 0>, <&uart-bam 1>;

		dma-names = "rx", "tx";

	};

Documentation/devicetree/bindings/dma/sirfsoc-dma.txt

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* CSR SiRFSoC DMA controller



See dma.txt first



Required properties:

- compatible: Should be "sirf,prima2-dmac" or "sirf,marco-dmac"

- reg: Should contain DMA registers location and length.

- interrupts: Should contain one interrupt shared by all channel

- #dma-cells: must be <1>. used to represent the number of integer

    cells in the dmas property of client device.

- clocks: clock required



Example:



Controller:

dmac0: dma-controller@b00b0000 {

	compatible = "sirf,prima2-dmac";

	reg = <0xb00b0000 0x10000>;

	interrupts = <12>;

	clocks = <&clks 24>;

	#dma-cells = <1>;

};





Client:

Fill the specific dma request line in dmas. In the below example, spi0 read

channel request line is 9 of the 2nd dma controller, while write channel uses

4 of the 2nd dma controller; spi1 read channel request line is 12 of the 1st

dma controller, while write channel uses 13 of the 1st dma controller:



spi0: spi@b00d0000 {

	compatible = "sirf,prima2-spi";

	dmas = <&dmac1 9>,

		<&dmac1 4>;

	dma-names = "rx", "tx";

};



spi1: spi@b0170000 {

	compatible = "sirf,prima2-spi";

	dmas = <&dmac0 12>,

		<&dmac0 13>;

	dma-names = "rx", "tx";

};

arch/arm/boot/dts/atlas6.dtsi

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@@ -271,6 +271,7 @@ 
				reg = <0xb00b0000 0x10000>;

				interrupts = <12>;

				clocks = <&clks 24>;

				#dma-cells = <1>;

			};



			dmac1: dma-controller@b0160000 {
@@ -279,6 +280,7 @@ 
				reg = <0xb0160000 0x10000>;

				interrupts = <13>;

				clocks = <&clks 25>;

				#dma-cells = <1>;

			};



			vip@b00C0000 {

arch/arm/boot/dts/prima2.dtsi

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@@ -287,6 +287,7 @@ 
				reg = <0xb00b0000 0x10000>;

				interrupts = <12>;

				clocks = <&clks 24>;

				#dma-cells = <1>;

			};



			dmac1: dma-controller@b0160000 {
@@ -295,6 +296,7 @@ 
				reg = <0xb0160000 0x10000>;

				interrupts = <13>;

				clocks = <&clks 25>;

				#dma-cells = <1>;

			};



			vip@b00C0000 {

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