Commit 6c45e480 authored by Evan Quan's avatar Evan Quan Committed by Alex Deucher
Browse files

drm/amd/powerplay: clear the swSMU code layer 



With this cleanup, the APIs from amdgpu_smu.c will map to
ASIC specific ones directly. Those can be shared around
all SMU V11/V12 ASICs will be put in smu_v11_0.c and
smu_v12_0.c respectively.

Signed-off-by: default avatarEvan Quan <evan.quan@amd.com>
Acked-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 18c1d3ce

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c

+21 −21
Original line number Diff line number Diff line
@@ -345,7 +345,7 @@ bool dm_pp_get_clock_levels_by_type( 
		/* Error in pplib. Provide default values. */

			return true;

		}

	} else if (adev->smu.funcs && adev->smu.funcs->get_clock_by_type) {

	} else if (adev->smu.ppt_funcs && adev->smu.ppt_funcs->get_clock_by_type) {

		if (smu_get_clock_by_type(&adev->smu,

					  dc_to_pp_clock_type(clk_type),

					  &pp_clks)) {
@@ -365,7 +365,7 @@ bool dm_pp_get_clock_levels_by_type( 
			validation_clks.memory_max_clock = 80000;

			validation_clks.level = 0;

		}

	} else if (adev->smu.funcs && adev->smu.funcs->get_max_high_clocks) {

	} else if (adev->smu.ppt_funcs && adev->smu.ppt_funcs->get_max_high_clocks) {

		if (smu_get_max_high_clocks(&adev->smu, &validation_clks)) {

			DRM_INFO("DM_PPLIB: Warning: using default validation clocks!\n");

			validation_clks.engine_max_clock = 72000;
@@ -506,8 +506,8 @@ bool dm_pp_apply_clock_for_voltage_request( 
		ret = adev->powerplay.pp_funcs->display_clock_voltage_request(

			adev->powerplay.pp_handle,

			&pp_clock_request);

	else if (adev->smu.funcs &&

		 adev->smu.funcs->display_clock_voltage_request)

	else if (adev->smu.ppt_funcs &&

		 adev->smu.ppt_funcs->display_clock_voltage_request)

		ret = smu_display_clock_voltage_request(&adev->smu,

							&pp_clock_request);

	if (ret)
@@ -527,7 +527,7 @@ bool dm_pp_get_static_clocks( 
		ret = adev->powerplay.pp_funcs->get_current_clocks(

			adev->powerplay.pp_handle,

			&pp_clk_info);

	else if (adev->smu.funcs)

	else if (adev->smu.ppt_funcs)

		ret = smu_get_current_clocks(&adev->smu, &pp_clk_info);

	if (ret)

		return false;
@@ -603,7 +603,7 @@ void pp_rv_set_pme_wa_enable(struct pp_smu *pp) 


	if (pp_funcs && pp_funcs->notify_smu_enable_pwe)

		pp_funcs->notify_smu_enable_pwe(pp_handle);

	else if (adev->smu.funcs)

	else if (adev->smu.ppt_funcs)

		smu_notify_smu_enable_pwe(&adev->smu);

}
@@ -717,10 +717,10 @@ enum pp_smu_status pp_nv_set_pme_wa_enable(struct pp_smu *pp) 
	struct amdgpu_device *adev = ctx->driver_context;

	struct smu_context *smu = &adev->smu;



	if (!smu->funcs)

	if (!smu->ppt_funcs)

		return PP_SMU_RESULT_UNSUPPORTED;



	/* 0: successful or smu.funcs->set_azalia_d3_pme = NULL;  1: fail */

	/* 0: successful or smu.ppt_funcs->set_azalia_d3_pme = NULL;  1: fail */

	if (smu_set_azalia_d3_pme(smu))

		return PP_SMU_RESULT_FAIL;
@@ -733,10 +733,10 @@ enum pp_smu_status pp_nv_set_display_count(struct pp_smu *pp, int count) 
	struct amdgpu_device *adev = ctx->driver_context;

	struct smu_context *smu = &adev->smu;



	if (!smu->funcs)

	if (!smu->ppt_funcs)

		return PP_SMU_RESULT_UNSUPPORTED;



	/* 0: successful or smu.funcs->set_display_count = NULL;  1: fail */

	/* 0: successful or smu.ppt_funcs->set_display_count = NULL;  1: fail */

	if (smu_set_display_count(smu, count))

		return PP_SMU_RESULT_FAIL;
@@ -749,10 +749,10 @@ enum pp_smu_status pp_nv_set_min_deep_sleep_dcfclk(struct pp_smu *pp, int mhz) 
	struct amdgpu_device *adev = ctx->driver_context;

	struct smu_context *smu = &adev->smu;



	if (!smu->funcs)

	if (!smu->ppt_funcs)

		return PP_SMU_RESULT_UNSUPPORTED;



	/* 0: successful or smu.funcs->set_deep_sleep_dcefclk = NULL;1: fail */

	/* 0: successful or smu.ppt_funcs->set_deep_sleep_dcefclk = NULL;1: fail */

	if (smu_set_deep_sleep_dcefclk(smu, mhz))

		return PP_SMU_RESULT_FAIL;
@@ -767,13 +767,13 @@ enum pp_smu_status pp_nv_set_hard_min_dcefclk_by_freq( 
	struct smu_context *smu = &adev->smu;

	struct pp_display_clock_request clock_req;



	if (!smu->funcs)

	if (!smu->ppt_funcs)

		return PP_SMU_RESULT_UNSUPPORTED;



	clock_req.clock_type = amd_pp_dcef_clock;

	clock_req.clock_freq_in_khz = mhz * 1000;



	/* 0: successful or smu.funcs->display_clock_voltage_request = NULL

	/* 0: successful or smu.ppt_funcs->display_clock_voltage_request = NULL

	 * 1: fail

	 */

	if (smu_display_clock_voltage_request(smu, &clock_req))
@@ -789,13 +789,13 @@ enum pp_smu_status pp_nv_set_hard_min_uclk_by_freq(struct pp_smu *pp, int mhz) 
	struct smu_context *smu = &adev->smu;

	struct pp_display_clock_request clock_req;



	if (!smu->funcs)

	if (!smu->ppt_funcs)

		return PP_SMU_RESULT_UNSUPPORTED;



	clock_req.clock_type = amd_pp_mem_clock;

	clock_req.clock_freq_in_khz = mhz * 1000;



	/* 0: successful or smu.funcs->display_clock_voltage_request = NULL

	/* 0: successful or smu.ppt_funcs->display_clock_voltage_request = NULL

	 * 1: fail

	 */

	if (smu_display_clock_voltage_request(smu, &clock_req))
@@ -825,7 +825,7 @@ enum pp_smu_status pp_nv_set_voltage_by_freq(struct pp_smu *pp, 
	struct smu_context *smu = &adev->smu;

	struct pp_display_clock_request clock_req;



	if (!smu->funcs)

	if (!smu->ppt_funcs)

		return PP_SMU_RESULT_UNSUPPORTED;



	switch (clock_id) {
@@ -843,7 +843,7 @@ enum pp_smu_status pp_nv_set_voltage_by_freq(struct pp_smu *pp, 
	}

	clock_req.clock_freq_in_khz = mhz * 1000;



	/* 0: successful or smu.funcs->display_clock_voltage_request = NULL

	/* 0: successful or smu.ppt_funcs->display_clock_voltage_request = NULL

	 * 1: fail

	 */

	if (smu_display_clock_voltage_request(smu, &clock_req))
@@ -859,10 +859,10 @@ enum pp_smu_status pp_nv_get_maximum_sustainable_clocks( 
	struct amdgpu_device *adev = ctx->driver_context;

	struct smu_context *smu = &adev->smu;



	if (!smu->funcs)

	if (!smu->ppt_funcs)

		return PP_SMU_RESULT_UNSUPPORTED;



	if (!smu->funcs->get_max_sustainable_clocks_by_dc)

	if (!smu->ppt_funcs->get_max_sustainable_clocks_by_dc)

		return PP_SMU_RESULT_UNSUPPORTED;



	if (!smu_get_max_sustainable_clocks_by_dc(smu, max_clocks))
@@ -924,7 +924,7 @@ enum pp_smu_status pp_rn_set_wm_ranges(struct pp_smu *pp, 
			wm_with_clock_ranges.wm_mcif_clocks_ranges;

	int32_t i;



	if (!smu->funcs)

	if (!smu->ppt_funcs)

		return PP_SMU_RESULT_UNSUPPORTED;



	wm_with_clock_ranges.num_wm_dmif_sets = ranges->num_reader_wm_sets;

drivers/gpu/drm/amd/powerplay/amdgpu_smu.c

+61 −54
Original line number Diff line number Diff line
@@ -31,6 +31,10 @@ 
#include "smu_v12_0.h"

#include "atom.h"

#include "amd_pcie.h"

#include "vega20_ppt.h"

#include "arcturus_ppt.h"

#include "navi10_ppt.h"

#include "renoir_ppt.h"



#undef __SMU_DUMMY_MAP

#define __SMU_DUMMY_MAP(type)	#type
@@ -703,23 +707,26 @@ static int smu_set_funcs(struct amdgpu_device *adev) 


	switch (adev->asic_type) {

	case CHIP_VEGA20:

		vega20_set_ppt_funcs(smu);

		break;

	case CHIP_NAVI10:

	case CHIP_NAVI14:

	case CHIP_NAVI12:

		navi10_set_ppt_funcs(smu);

		break;

	case CHIP_ARCTURUS:

		if (adev->pm.pp_feature & PP_OVERDRIVE_MASK)

			smu->od_enabled = true;

		smu_v11_0_set_smu_funcs(smu);

		arcturus_set_ppt_funcs(smu);

		break;

	case CHIP_RENOIR:

		if (adev->pm.pp_feature & PP_OVERDRIVE_MASK)

			smu->od_enabled = true;

		smu_v12_0_set_smu_funcs(smu);

		renoir_set_ppt_funcs(smu);

		break;

	default:

		return -EINVAL;

	}



	if (adev->pm.pp_feature & PP_OVERDRIVE_MASK)

		smu->od_enabled = true;



	return 0;

}
@@ -1177,16 +1184,16 @@ static int smu_start_smc_engine(struct smu_context *smu) 


	if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {

		if (adev->asic_type < CHIP_NAVI10) {

			if (smu->funcs->load_microcode) {

				ret = smu->funcs->load_microcode(smu);

			if (smu->ppt_funcs->load_microcode) {

				ret = smu->ppt_funcs->load_microcode(smu);

				if (ret)

					return ret;

			}

		}

	}



	if (smu->funcs->check_fw_status) {

		ret = smu->funcs->check_fw_status(smu);

	if (smu->ppt_funcs->check_fw_status) {

		ret = smu->ppt_funcs->check_fw_status(smu);

		if (ret)

			pr_err("SMC is not ready\n");

	}
@@ -1397,8 +1404,8 @@ int smu_display_configuration_change(struct smu_context *smu, 


	mutex_lock(&smu->mutex);



	if (smu->funcs->set_deep_sleep_dcefclk)

		smu->funcs->set_deep_sleep_dcefclk(smu,

	if (smu->ppt_funcs->set_deep_sleep_dcefclk)

		smu->ppt_funcs->set_deep_sleep_dcefclk(smu,

				display_config->min_dcef_deep_sleep_set_clk / 100);



	for (index = 0; index < display_config->num_path_including_non_display; index++) {
@@ -1952,8 +1959,8 @@ int smu_load_microcode(struct smu_context *smu) 


	mutex_lock(&smu->mutex);



	if (smu->funcs->load_microcode)

		ret = smu->funcs->load_microcode(smu);

	if (smu->ppt_funcs->load_microcode)

		ret = smu->ppt_funcs->load_microcode(smu);



	mutex_unlock(&smu->mutex);
@@ -1966,8 +1973,8 @@ int smu_check_fw_status(struct smu_context *smu) 


	mutex_lock(&smu->mutex);



	if (smu->funcs->check_fw_status)

		ret = smu->funcs->check_fw_status(smu);

	if (smu->ppt_funcs->check_fw_status)

		ret = smu->ppt_funcs->check_fw_status(smu);



	mutex_unlock(&smu->mutex);
@@ -1980,8 +1987,8 @@ int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled) 


	mutex_lock(&smu->mutex);



	if (smu->funcs->set_gfx_cgpg)

		ret = smu->funcs->set_gfx_cgpg(smu, enabled);

	if (smu->ppt_funcs->set_gfx_cgpg)

		ret = smu->ppt_funcs->set_gfx_cgpg(smu, enabled);



	mutex_unlock(&smu->mutex);
@@ -1994,8 +2001,8 @@ int smu_set_fan_speed_rpm(struct smu_context *smu, uint32_t speed) 


	mutex_lock(&smu->mutex);



	if (smu->funcs->set_fan_speed_rpm)

		ret = smu->funcs->set_fan_speed_rpm(smu, speed);

	if (smu->ppt_funcs->set_fan_speed_rpm)

		ret = smu->ppt_funcs->set_fan_speed_rpm(smu, speed);



	mutex_unlock(&smu->mutex);
@@ -2027,8 +2034,8 @@ int smu_set_power_limit(struct smu_context *smu, uint32_t limit) 


	mutex_lock(&smu->mutex);



	if (smu->funcs->set_power_limit)

		ret = smu->funcs->set_power_limit(smu, limit);

	if (smu->ppt_funcs->set_power_limit)

		ret = smu->ppt_funcs->set_power_limit(smu, limit);



	mutex_unlock(&smu->mutex);
@@ -2149,8 +2156,8 @@ int smu_get_fan_control_mode(struct smu_context *smu) 


	mutex_lock(&smu->mutex);



	if (smu->funcs->get_fan_control_mode)

		ret = smu->funcs->get_fan_control_mode(smu);

	if (smu->ppt_funcs->get_fan_control_mode)

		ret = smu->ppt_funcs->get_fan_control_mode(smu);



	mutex_unlock(&smu->mutex);
@@ -2163,8 +2170,8 @@ int smu_set_fan_control_mode(struct smu_context *smu, int value) 


	mutex_lock(&smu->mutex);



	if (smu->funcs->set_fan_control_mode)

		ret = smu->funcs->set_fan_control_mode(smu, value);

	if (smu->ppt_funcs->set_fan_control_mode)

		ret = smu->ppt_funcs->set_fan_control_mode(smu, value);



	mutex_unlock(&smu->mutex);
@@ -2191,8 +2198,8 @@ int smu_set_fan_speed_percent(struct smu_context *smu, uint32_t speed) 


	mutex_lock(&smu->mutex);



	if (smu->funcs->set_fan_speed_percent)

		ret = smu->funcs->set_fan_speed_percent(smu, speed);

	if (smu->ppt_funcs->set_fan_speed_percent)

		ret = smu->ppt_funcs->set_fan_speed_percent(smu, speed);



	mutex_unlock(&smu->mutex);
@@ -2219,8 +2226,8 @@ int smu_set_deep_sleep_dcefclk(struct smu_context *smu, int clk) 


	mutex_lock(&smu->mutex);



	if (smu->funcs->set_deep_sleep_dcefclk)

		ret = smu->funcs->set_deep_sleep_dcefclk(smu, clk);

	if (smu->ppt_funcs->set_deep_sleep_dcefclk)

		ret = smu->ppt_funcs->set_deep_sleep_dcefclk(smu, clk);



	mutex_unlock(&smu->mutex);
@@ -2233,8 +2240,8 @@ int smu_set_active_display_count(struct smu_context *smu, uint32_t count) 


	mutex_lock(&smu->mutex);



	if (smu->funcs->set_active_display_count)

		ret = smu->funcs->set_active_display_count(smu, count);

	if (smu->ppt_funcs->set_active_display_count)

		ret = smu->ppt_funcs->set_active_display_count(smu, count);



	mutex_unlock(&smu->mutex);
@@ -2249,8 +2256,8 @@ int smu_get_clock_by_type(struct smu_context *smu, 


	mutex_lock(&smu->mutex);



	if (smu->funcs->get_clock_by_type)

		ret = smu->funcs->get_clock_by_type(smu, type, clocks);

	if (smu->ppt_funcs->get_clock_by_type)

		ret = smu->ppt_funcs->get_clock_by_type(smu, type, clocks);



	mutex_unlock(&smu->mutex);
@@ -2264,8 +2271,8 @@ int smu_get_max_high_clocks(struct smu_context *smu, 


	mutex_lock(&smu->mutex);



	if (smu->funcs->get_max_high_clocks)

		ret = smu->funcs->get_max_high_clocks(smu, clocks);

	if (smu->ppt_funcs->get_max_high_clocks)

		ret = smu->ppt_funcs->get_max_high_clocks(smu, clocks);



	mutex_unlock(&smu->mutex);
@@ -2312,8 +2319,8 @@ int smu_display_clock_voltage_request(struct smu_context *smu, 


	mutex_lock(&smu->mutex);



	if (smu->funcs->display_clock_voltage_request)

		ret = smu->funcs->display_clock_voltage_request(smu, clock_req);

	if (smu->ppt_funcs->display_clock_voltage_request)

		ret = smu->ppt_funcs->display_clock_voltage_request(smu, clock_req);



	mutex_unlock(&smu->mutex);
@@ -2341,8 +2348,8 @@ int smu_notify_smu_enable_pwe(struct smu_context *smu) 


	mutex_lock(&smu->mutex);



	if (smu->funcs->notify_smu_enable_pwe)

		ret = smu->funcs->notify_smu_enable_pwe(smu);

	if (smu->ppt_funcs->notify_smu_enable_pwe)

		ret = smu->ppt_funcs->notify_smu_enable_pwe(smu);



	mutex_unlock(&smu->mutex);
@@ -2356,8 +2363,8 @@ int smu_set_xgmi_pstate(struct smu_context *smu, 


	mutex_lock(&smu->mutex);



	if (smu->funcs->set_xgmi_pstate)

		ret = smu->funcs->set_xgmi_pstate(smu, pstate);

	if (smu->ppt_funcs->set_xgmi_pstate)

		ret = smu->ppt_funcs->set_xgmi_pstate(smu, pstate);



	mutex_unlock(&smu->mutex);
@@ -2370,8 +2377,8 @@ int smu_set_azalia_d3_pme(struct smu_context *smu) 


	mutex_lock(&smu->mutex);



	if (smu->funcs->set_azalia_d3_pme)

		ret = smu->funcs->set_azalia_d3_pme(smu);

	if (smu->ppt_funcs->set_azalia_d3_pme)

		ret = smu->ppt_funcs->set_azalia_d3_pme(smu);



	mutex_unlock(&smu->mutex);
@@ -2384,8 +2391,8 @@ bool smu_baco_is_support(struct smu_context *smu) 


	mutex_lock(&smu->mutex);



	if (smu->funcs->baco_is_support)

		ret = smu->funcs->baco_is_support(smu);

	if (smu->ppt_funcs->baco_is_support)

		ret = smu->ppt_funcs->baco_is_support(smu);



	mutex_unlock(&smu->mutex);
@@ -2394,11 +2401,11 @@ bool smu_baco_is_support(struct smu_context *smu) 


int smu_baco_get_state(struct smu_context *smu, enum smu_baco_state *state)

{

	if (smu->funcs->baco_get_state)

	if (smu->ppt_funcs->baco_get_state)

		return -EINVAL;



	mutex_lock(&smu->mutex);

	*state = smu->funcs->baco_get_state(smu);

	*state = smu->ppt_funcs->baco_get_state(smu);

	mutex_unlock(&smu->mutex);



	return 0;
@@ -2410,8 +2417,8 @@ int smu_baco_reset(struct smu_context *smu) 


	mutex_lock(&smu->mutex);



	if (smu->funcs->baco_reset)

		ret = smu->funcs->baco_reset(smu);

	if (smu->ppt_funcs->baco_reset)

		ret = smu->ppt_funcs->baco_reset(smu);



	mutex_unlock(&smu->mutex);
@@ -2424,8 +2431,8 @@ int smu_mode2_reset(struct smu_context *smu) 


	mutex_lock(&smu->mutex);



	if (smu->funcs->mode2_reset)

		ret = smu->funcs->mode2_reset(smu);

	if (smu->ppt_funcs->mode2_reset)

		ret = smu->ppt_funcs->mode2_reset(smu);



	mutex_unlock(&smu->mutex);
@@ -2439,8 +2446,8 @@ int smu_get_max_sustainable_clocks_by_dc(struct smu_context *smu, 


	mutex_lock(&smu->mutex);



	if (smu->funcs->get_max_sustainable_clocks_by_dc)

		ret = smu->funcs->get_max_sustainable_clocks_by_dc(smu, max_clocks);

	if (smu->ppt_funcs->get_max_sustainable_clocks_by_dc)

		ret = smu->ppt_funcs->get_max_sustainable_clocks_by_dc(smu, max_clocks);



	mutex_unlock(&smu->mutex);

drivers/gpu/drm/amd/powerplay/arcturus_ppt.c

+50 −1
Original line number Diff line number Diff line
@@ -1048,7 +1048,7 @@ static int arcturus_read_sensor(struct smu_context *smu, 
		*size = 4;

		break;

	default:

		ret = smu_smc_read_sensor(smu, sensor, data, size);

		ret = smu_v11_0_read_sensor(smu, sensor, data, size);

	}

	mutex_unlock(&smu->sensor_lock);
@@ -1964,6 +1964,55 @@ static const struct pptable_funcs arcturus_ppt_funcs = { 
	.get_power_limit = arcturus_get_power_limit,

	.is_dpm_running = arcturus_is_dpm_running,

	.dpm_set_uvd_enable = arcturus_dpm_set_uvd_enable,

	.init_microcode = smu_v11_0_init_microcode,

	.load_microcode = smu_v11_0_load_microcode,

	.init_smc_tables = smu_v11_0_init_smc_tables,

	.fini_smc_tables = smu_v11_0_fini_smc_tables,

	.init_power = smu_v11_0_init_power,

	.fini_power = smu_v11_0_fini_power,

	.check_fw_status = smu_v11_0_check_fw_status,

	.setup_pptable = smu_v11_0_setup_pptable,

	.get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,

	.get_clk_info_from_vbios = smu_v11_0_get_clk_info_from_vbios,

	.check_pptable = smu_v11_0_check_pptable,

	.parse_pptable = smu_v11_0_parse_pptable,

	.populate_smc_tables = smu_v11_0_populate_smc_pptable,

	.check_fw_version = smu_v11_0_check_fw_version,

	.write_pptable = smu_v11_0_write_pptable,

	.set_min_dcef_deep_sleep = smu_v11_0_set_min_dcef_deep_sleep,

	.set_tool_table_location = smu_v11_0_set_tool_table_location,

	.notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,

	.system_features_control = smu_v11_0_system_features_control,

	.send_smc_msg = smu_v11_0_send_msg,

	.send_smc_msg_with_param = smu_v11_0_send_msg_with_param,

	.read_smc_arg = smu_v11_0_read_arg,

	.init_display_count = smu_v11_0_init_display_count,

	.set_allowed_mask = smu_v11_0_set_allowed_mask,

	.get_enabled_mask = smu_v11_0_get_enabled_mask,

	.notify_display_change = smu_v11_0_notify_display_change,

	.set_power_limit = smu_v11_0_set_power_limit,

	.get_current_clk_freq = smu_v11_0_get_current_clk_freq,

	.init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,

	.start_thermal_control = smu_v11_0_start_thermal_control,

	.stop_thermal_control = smu_v11_0_stop_thermal_control,

	.set_deep_sleep_dcefclk = smu_v11_0_set_deep_sleep_dcefclk,

	.display_clock_voltage_request = smu_v11_0_display_clock_voltage_request,

	.get_fan_control_mode = smu_v11_0_get_fan_control_mode,

	.set_fan_control_mode = smu_v11_0_set_fan_control_mode,

	.set_fan_speed_percent = smu_v11_0_set_fan_speed_percent,

	.set_fan_speed_rpm = smu_v11_0_set_fan_speed_rpm,

	.set_xgmi_pstate = smu_v11_0_set_xgmi_pstate,

	.gfx_off_control = smu_v11_0_gfx_off_control,

	.register_irq_handler = smu_v11_0_register_irq_handler,

	.set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme,

	.get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc,

	.baco_is_support= smu_v11_0_baco_is_support,

	.baco_get_state = smu_v11_0_baco_get_state,

	.baco_set_state = smu_v11_0_baco_set_state,

	.baco_reset = smu_v11_0_baco_reset,

	.get_dpm_ultimate_freq = smu_v11_0_get_dpm_ultimate_freq,

	.set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,

	.override_pcie_parameters = smu_v11_0_override_pcie_parameters,

};



void arcturus_set_ppt_funcs(struct smu_context *smu)

drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h

+1 −8
Original line number Diff line number Diff line
@@ -347,7 +347,6 @@ struct smu_context 
	struct amdgpu_device            *adev;

	struct amdgpu_irq_src		*irq_source;



	const struct smu_funcs		*funcs;

	const struct pptable_funcs	*ppt_funcs;

	struct mutex			mutex;

	struct mutex			sensor_lock;
@@ -471,16 +470,12 @@ struct pptable_funcs { 
	int (*set_df_cstate)(struct smu_context *smu, enum pp_df_cstate state);

	int (*update_pcie_parameters)(struct smu_context *smu, uint32_t pcie_gen_cap, uint32_t pcie_width_cap);

	int (*get_dpm_clock_table)(struct smu_context *smu, struct dpm_clocks *clock_table);

};



struct smu_funcs

{

	int (*init_microcode)(struct smu_context *smu);

	int (*load_microcode)(struct smu_context *smu);

	int (*init_smc_tables)(struct smu_context *smu);

	int (*fini_smc_tables)(struct smu_context *smu);

	int (*init_power)(struct smu_context *smu);

	int (*fini_power)(struct smu_context *smu);

	int (*load_microcode)(struct smu_context *smu);

	int (*check_fw_status)(struct smu_context *smu);

	int (*setup_pptable)(struct smu_context *smu);

	int (*get_vbios_bootup_values)(struct smu_context *smu);
@@ -510,8 +505,6 @@ struct smu_funcs 
	int (*init_max_sustainable_clocks)(struct smu_context *smu);

	int (*start_thermal_control)(struct smu_context *smu);

	int (*stop_thermal_control)(struct smu_context *smu);

	int (*read_sensor)(struct smu_context *smu, enum amd_pp_sensors sensor,

			   void *data, uint32_t *size);

	int (*set_deep_sleep_dcefclk)(struct smu_context *smu, uint32_t clk);

	int (*set_active_display_count)(struct smu_context *smu, uint32_t count);

	int (*store_cc6_data)(struct smu_context *smu, uint32_t separation_time,

drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h

+119 −1
Original line number Diff line number Diff line
@@ -130,6 +130,124 @@ enum smu_v11_0_baco_seq { 
	BACO_SEQ_COUNT,

};



void smu_v11_0_set_smu_funcs(struct smu_context *smu);

int smu_v11_0_init_microcode(struct smu_context *smu);



int smu_v11_0_load_microcode(struct smu_context *smu);



int smu_v11_0_init_smc_tables(struct smu_context *smu);



int smu_v11_0_fini_smc_tables(struct smu_context *smu);



int smu_v11_0_init_power(struct smu_context *smu);



int smu_v11_0_fini_power(struct smu_context *smu);



int smu_v11_0_check_fw_status(struct smu_context *smu);



int smu_v11_0_setup_pptable(struct smu_context *smu);



int smu_v11_0_get_vbios_bootup_values(struct smu_context *smu);



int smu_v11_0_get_clk_info_from_vbios(struct smu_context *smu);



int smu_v11_0_check_pptable(struct smu_context *smu);



int smu_v11_0_parse_pptable(struct smu_context *smu);



int smu_v11_0_populate_smc_pptable(struct smu_context *smu);



int smu_v11_0_check_fw_version(struct smu_context *smu);



int smu_v11_0_write_pptable(struct smu_context *smu);



int smu_v11_0_set_min_dcef_deep_sleep(struct smu_context *smu);



int smu_v11_0_set_tool_table_location(struct smu_context *smu);



int smu_v11_0_notify_memory_pool_location(struct smu_context *smu);



int smu_v11_0_system_features_control(struct smu_context *smu,

					     bool en);



int smu_v11_0_send_msg(struct smu_context *smu, uint16_t msg);



int

smu_v11_0_send_msg_with_param(struct smu_context *smu, uint16_t msg,

			      uint32_t param);



int smu_v11_0_read_arg(struct smu_context *smu, uint32_t *arg);



int smu_v11_0_init_display_count(struct smu_context *smu, uint32_t count);



int smu_v11_0_set_allowed_mask(struct smu_context *smu);



int smu_v11_0_get_enabled_mask(struct smu_context *smu,

				      uint32_t *feature_mask, uint32_t num);



int smu_v11_0_notify_display_change(struct smu_context *smu);



int smu_v11_0_set_power_limit(struct smu_context *smu, uint32_t n);



int smu_v11_0_get_current_clk_freq(struct smu_context *smu,

					  enum smu_clk_type clk_id,

					  uint32_t *value);



int smu_v11_0_init_max_sustainable_clocks(struct smu_context *smu);



int smu_v11_0_start_thermal_control(struct smu_context *smu);



int smu_v11_0_stop_thermal_control(struct smu_context *smu);



int smu_v11_0_read_sensor(struct smu_context *smu,

				 enum amd_pp_sensors sensor,

				 void *data, uint32_t *size);



int smu_v11_0_set_deep_sleep_dcefclk(struct smu_context *smu, uint32_t clk);



int

smu_v11_0_display_clock_voltage_request(struct smu_context *smu,

					struct pp_display_clock_request

					*clock_req);



uint32_t

smu_v11_0_get_fan_control_mode(struct smu_context *smu);



int

smu_v11_0_set_fan_control_mode(struct smu_context *smu,

			       uint32_t mode);



int

smu_v11_0_set_fan_speed_percent(struct smu_context *smu, uint32_t speed);



int smu_v11_0_set_fan_speed_rpm(struct smu_context *smu,

				       uint32_t speed);



int smu_v11_0_set_xgmi_pstate(struct smu_context *smu,

				     uint32_t pstate);



int smu_v11_0_gfx_off_control(struct smu_context *smu, bool enable);



int smu_v11_0_register_irq_handler(struct smu_context *smu);



int smu_v11_0_set_azalia_d3_pme(struct smu_context *smu);



int smu_v11_0_get_max_sustainable_clocks_by_dc(struct smu_context *smu,

		struct pp_smu_nv_clock_table *max_clocks);



bool smu_v11_0_baco_is_support(struct smu_context *smu);



enum smu_baco_state smu_v11_0_baco_get_state(struct smu_context *smu);



int smu_v11_0_baco_set_state(struct smu_context *smu, enum smu_baco_state state);



int smu_v11_0_baco_reset(struct smu_context *smu);



int smu_v11_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,

						 uint32_t *min, uint32_t *max);



int smu_v11_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type,

			    uint32_t min, uint32_t max);



int smu_v11_0_override_pcie_parameters(struct smu_context *smu);



#endif

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