ARM: owl: smp: Drop owl_secondary_boot()

obj-${CONFIG_SMP} += platsmp.o headsmp.o

AFLAGS_headsmp.o := -Wa,-march=armv7-a

obj-${CONFIG_SMP} += platsmp.o

/*

 * Copyright 2012 Actions Semi Inc.

 * Author: Actions Semi, Inc.

 *

 * Copyright (c) 2017 Andreas Färber

 *

 * This program is free software; you can redistribute  it and/or modify it

 * under  the terms of  the GNU General  Public License as published by the

 * Free Software Foundation;  either version 2 of the  License, or (at your

 * option) any later version.

 */

#include <linux/linkage.h>

#include <linux/init.h>

ENTRY(owl_v7_invalidate_l1)

	mov	r0, #0

	mcr	p15, 0, r0, c7, c5, 0	@ invalidate I cache

	mcr	p15, 2, r0, c0, c0, 0

	mrc	p15, 1, r0, c0, c0, 0

	ldr	r1, =0x7fff

	and	r2, r1, r0, lsr #13

	ldr	r1, =0x3ff

	and	r3, r1, r0, lsr #3	@ NumWays - 1

	add	r2, r2, #1		@ NumSets

	and	r0, r0, #0x7

	add	r0, r0, #4	@ SetShift

	clz	r1, r3		@ WayShift

	add	r4, r3, #1	@ NumWays

1:	sub	r2, r2, #1	@ NumSets--

	mov	r3, r4		@ Temp = NumWays

2:	subs	r3, r3, #1	@ Temp--

	mov	r5, r3, lsl r1

	mov	r6, r2, lsl r0

	orr	r5, r5, r6	@ Reg = (Temp<<WayShift)|(NumSets<<SetShift)

	mcr	p15, 0, r5, c7, c6, 2

	bgt	2b

	cmp	r2, #0

	bgt	1b

	dsb

	isb

	mov	pc, lr

ENDPROC(owl_v7_invalidate_l1)

ENTRY(owl_secondary_startup)

	bl	owl_v7_invalidate_l1

	b	secondary_startup

	/* wait for CPUx to run to WFE instruction */

	udelay(200);

	writel(__pa_symbol(owl_secondary_startup),

	writel(__pa_symbol(secondary_startup),

	       timer_base_addr + OWL_CPU1_ADDR + (cpu - 1) * 4);

	writel(OWL_CPUx_FLAG_BOOT,

	       timer_base_addr + OWL_CPU1_FLAG + (cpu - 1) * 4);