Commit 6c19156e authored by Heiner Kallweit's avatar Heiner Kallweit Committed by David S. Miller
Browse files

r8169: remove callback hw_start from struct rtl_cfg_info 



After the latest changes we don't need separate functions
rtl_hw_start_8168 and rtl_hw_start_8101 any longer. This allows us to
simplify the code. For this change we need to move rtl_hw_start() and
rtl_hw_start_8169(). rtl_hw_start_8169() is unchanged.

Signed-off-by: default avatarHeiner Kallweit <hkallweit1@gmail.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent bc73241e

drivers/net/ethernet/realtek/r8169_main.c

+53 −64
Original line number Diff line number Diff line
@@ -652,8 +652,6 @@ struct rtl8169_private { 
	const struct rtl_coalesce_info *coalesce_info;

	struct clk *clk;



	void (*hw_start)(struct rtl8169_private *tp);



	struct {

		DECLARE_BITMAP(flags, RTL_FLAG_MAX);

		struct mutex mutex;
@@ -4206,56 +4204,6 @@ static void rtl_set_rx_mode(struct net_device *dev) 
	RTL_W32(tp, RxConfig, tmp);

}



static void rtl_hw_start(struct  rtl8169_private *tp)

{

	rtl_unlock_config_regs(tp);



	tp->cp_cmd &= CPCMD_MASK;

	RTL_W16(tp, CPlusCmd, tp->cp_cmd);



	tp->hw_start(tp);



	rtl_set_rx_max_size(tp);

	rtl_set_rx_tx_desc_registers(tp);

	rtl_lock_config_regs(tp);



	/* disable interrupt coalescing */

	RTL_W16(tp, IntrMitigate, 0x0000);

	/* Initially a 10 us delay. Turned it into a PCI commit. - FR */

	RTL_R8(tp, IntrMask);

	RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb);

	rtl_init_rxcfg(tp);

	rtl_set_tx_config_registers(tp);



	rtl_set_rx_mode(tp->dev);

	/* no early-rx interrupts */

	RTL_W16(tp, MultiIntr, RTL_R16(tp, MultiIntr) & 0xf000);

	rtl_irq_enable(tp);

}



static void rtl_hw_start_8169(struct rtl8169_private *tp)

{

	if (tp->mac_version == RTL_GIGA_MAC_VER_05)

		pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);



	RTL_W8(tp, EarlyTxThres, NoEarlyTx);



	tp->cp_cmd |= PCIMulRW;



	if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||

	    tp->mac_version == RTL_GIGA_MAC_VER_03) {

		netif_dbg(tp, drv, tp->dev,

			  "Set MAC Reg C+CR Offset 0xe0. Bit 3 and Bit 14 MUST be 1\n");

		tp->cp_cmd |= (1 << 14);

	}



	RTL_W16(tp, CPlusCmd, tp->cp_cmd);



	rtl8169_set_magic_reg(tp, tp->mac_version);



	RTL_W32(tp, RxMissed, 0);

}



DECLARE_RTL_COND(rtl_csiar_cond)

{

	return RTL_R32(tp, CSIAR) & CSIAR_FLAG;
@@ -5121,13 +5069,6 @@ static void rtl_hw_config(struct rtl8169_private *tp) 
}



static void rtl_hw_start_8168(struct rtl8169_private *tp)

{

	RTL_W8(tp, MaxTxPacketSize, TxPacketMax);



	rtl_hw_config(tp);

}



static void rtl_hw_start_8101(struct rtl8169_private *tp)

{

	if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||

	    tp->mac_version == RTL_GIGA_MAC_VER_16)
@@ -5139,6 +5080,59 @@ static void rtl_hw_start_8101(struct rtl8169_private *tp) 
	rtl_hw_config(tp);

}



static void rtl_hw_start_8169(struct rtl8169_private *tp)

{

	if (tp->mac_version == RTL_GIGA_MAC_VER_05)

		pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);



	RTL_W8(tp, EarlyTxThres, NoEarlyTx);



	tp->cp_cmd |= PCIMulRW;



	if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||

	    tp->mac_version == RTL_GIGA_MAC_VER_03) {

		netif_dbg(tp, drv, tp->dev,

			  "Set MAC Reg C+CR Offset 0xe0. Bit 3 and Bit 14 MUST be 1\n");

		tp->cp_cmd |= (1 << 14);

	}



	RTL_W16(tp, CPlusCmd, tp->cp_cmd);



	rtl8169_set_magic_reg(tp, tp->mac_version);



	RTL_W32(tp, RxMissed, 0);

}



static void rtl_hw_start(struct  rtl8169_private *tp)

{

	rtl_unlock_config_regs(tp);



	tp->cp_cmd &= CPCMD_MASK;

	RTL_W16(tp, CPlusCmd, tp->cp_cmd);



	if (tp->mac_version <= RTL_GIGA_MAC_VER_06)

		rtl_hw_start_8169(tp);

	else

		rtl_hw_start_8168(tp);



	rtl_set_rx_max_size(tp);

	rtl_set_rx_tx_desc_registers(tp);

	rtl_lock_config_regs(tp);



	/* disable interrupt coalescing */

	RTL_W16(tp, IntrMitigate, 0x0000);

	/* Initially a 10 us delay. Turned it into a PCI commit. - FR */

	RTL_R8(tp, IntrMask);

	RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb);

	rtl_init_rxcfg(tp);

	rtl_set_tx_config_registers(tp);



	rtl_set_rx_mode(tp->dev);

	/* no early-rx interrupts */

	RTL_W16(tp, MultiIntr, RTL_R16(tp, MultiIntr) & 0xf000);

	rtl_irq_enable(tp);

}



static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)

{

	struct rtl8169_private *tp = netdev_priv(dev);
@@ -6466,22 +6460,18 @@ static const struct net_device_ops rtl_netdev_ops = { 
};



static const struct rtl_cfg_info {

	void (*hw_start)(struct rtl8169_private *tp);

	unsigned int has_gmii:1;

	const struct rtl_coalesce_info *coalesce_info;

} rtl_cfg_infos [] = {

	[RTL_CFG_0] = {

		.hw_start	= rtl_hw_start_8169,

		.has_gmii	= 1,

		.coalesce_info	= rtl_coalesce_info_8169,

	},

	[RTL_CFG_1] = {

		.hw_start	= rtl_hw_start_8168,

		.has_gmii	= 1,

		.coalesce_info	= rtl_coalesce_info_8168_8136,

	},

	[RTL_CFG_2] = {

		.hw_start	= rtl_hw_start_8101,

		.coalesce_info	= rtl_coalesce_info_8168_8136,

	}

};
@@ -6860,7 +6850,6 @@ static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 
	dev->max_mtu = jumbo_max;



	rtl_set_irq_mask(tp);

	tp->hw_start = cfg->hw_start;

	tp->coalesce_info = cfg->coalesce_info;



	tp->fw_name = rtl_chip_infos[chipset].fw_name;

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