Commit 6be7adb3 authored by Christian König's avatar Christian König Committed by Alex Deucher
Browse files

drm/amdgpu: increase fragmentation size for Vega10 v2 



The fragment bits work differently for Vega10 compared to previous generations.

Increase the fragment size to 2MB for now to better handle that.

v2: handle the hardware setup as well

Signed-off-by: default avatarChristian König <christian.koenig@amd.com>
Reviewed-and-tested-by: default avatarFelix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 07306b4f

drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c

+3 −2
Original line number Diff line number Diff line
@@ -589,7 +589,8 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file 
		dev_info.virtual_address_offset = AMDGPU_VA_RESERVED_SIZE;

		dev_info.virtual_address_max = (uint64_t)adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE;

		dev_info.virtual_address_alignment = max((int)PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE);

		dev_info.pte_fragment_size = (1 << AMDGPU_LOG2_PAGES_PER_FRAG) *

		dev_info.pte_fragment_size =

			(1 << AMDGPU_LOG2_PAGES_PER_FRAG(adev)) *

			AMDGPU_GPU_PAGE_SIZE;

		dev_info.gart_page_size = AMDGPU_GPU_PAGE_SIZE;

drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c

+3 −2
Original line number Diff line number Diff line
@@ -1381,8 +1381,9 @@ static int amdgpu_vm_frag_ptes(struct amdgpu_pte_update_params *params, 
	 */



	/* SI and newer are optimized for 64KB */

	uint64_t frag_flags = AMDGPU_PTE_FRAG(AMDGPU_LOG2_PAGES_PER_FRAG);

	uint64_t frag_align = 1 << AMDGPU_LOG2_PAGES_PER_FRAG;

	unsigned pages_per_frag = AMDGPU_LOG2_PAGES_PER_FRAG(params->adev);

	uint64_t frag_flags = AMDGPU_PTE_FRAG(pages_per_frag);

	uint64_t frag_align = 1 << pages_per_frag;



	uint64_t frag_start = ALIGN(start, frag_align);

	uint64_t frag_end = end & ~(frag_align - 1);

drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h

+3 −1
Original line number Diff line number Diff line
@@ -51,7 +51,9 @@ struct amdgpu_bo_list_entry; 
#define AMDGPU_VM_PTB_ALIGN_SIZE   32768



/* LOG2 number of continuous pages for the fragment field */

#define AMDGPU_LOG2_PAGES_PER_FRAG 4

#define AMDGPU_LOG2_PAGES_PER_FRAG(adev) \

	((adev)->asic_type < CHIP_VEGA10 ? 4 : \

	 (adev)->vm_manager.block_size)



#define AMDGPU_PTE_VALID	(1ULL << 0)

#define AMDGPU_PTE_SYSTEM	(1ULL << 1)

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c

+3 −1
Original line number Diff line number Diff line
@@ -129,7 +129,7 @@ static void gfxhub_v1_0_init_cache_regs(struct amdgpu_device *adev) 
	/* Setup L2 cache */

	tmp = RREG32_SOC15(GC, 0, mmVM_L2_CNTL);

	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);

	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0);

	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1);

	/* XXX for emulation, Refer to closed source code.*/

	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE,

			    0);
@@ -144,6 +144,8 @@ static void gfxhub_v1_0_init_cache_regs(struct amdgpu_device *adev) 
	WREG32_SOC15(GC, 0, mmVM_L2_CNTL2, tmp);



	tmp = mmVM_L2_CNTL3_DEFAULT;

	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 12);

	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, 9);

	WREG32_SOC15(GC, 0, mmVM_L2_CNTL3, tmp);



	tmp = mmVM_L2_CNTL4_DEFAULT;

drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c

+3 −1
Original line number Diff line number Diff line
@@ -143,7 +143,7 @@ static void mmhub_v1_0_init_cache_regs(struct amdgpu_device *adev) 
	/* Setup L2 cache */

	tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL);

	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);

	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0);

	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1);

	/* XXX for emulation, Refer to closed source code.*/

	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE,

			    0);
@@ -158,6 +158,8 @@ static void mmhub_v1_0_init_cache_regs(struct amdgpu_device *adev) 
	WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL2, tmp);



	tmp = mmVM_L2_CNTL3_DEFAULT;

	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 12);

	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, 9);

	WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL3, tmp);



	tmp = mmVM_L2_CNTL4_DEFAULT;

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