Commit 6bb340c7 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux 

Pull drm fixes from Dave Airlie:
 "Just regular fixes, bunch from intel, quieting some of the over
  zealous power warnings, and the rest just misc.

  I've got another pull with the remaining dma-buf bits, since the vmap
  bits are in your tree now.  I'll send tomorrow just to space things
  out a bit."

* 'drm-fixes' of git://people.freedesktop.org/~airlied/linux: (22 commits)
  drm/edid/quirks: ViewSonic VA2026w
  drm/udl: remove unused variables.
  drm/radeon: fix XFX quirk
  drm: Use stdint types for consistency
  drm: Constify params to format_check() and framebuffer_checks()
  drm/radeon: fix typo in trinity tiling setup
  drm/udl: unlock before returning in udl_gem_mmap()
  radeon: make radeon_cs_update_pages static.
  drm/i915: tune down the noise of the RP irq limit fail
  drm/i915: Remove the error message for unbinding pinned buffers
  drm/i915: Limit page allocations to lowmem (dma32) for i965
  drm/i915: always use RPNSWREQ for turbo change requests
  drm/i915: reject doubleclocked cea modes on dp
  drm/i915: Adding TV Out Missing modes.
  drm/i915: wait for a vblank to pass after tv detect
  drm/i915: no lvds quirk for HP t5740e Thin Client
  drm/i915: enable vdd when switching off the eDP panel
  drm/i915: Fix PCH PLL assertions to not assume CRTC:PLL relationship
  drm/i915: Always update RPS interrupts thresholds along with frequency
  drm/i915: properly handle interlaced bit for sdvo dtd conversion
  ...
parents a70f35af bc42aabc

drivers/gpu/drm/drm_crtc.c

+4 −4
Original line number Diff line number Diff line
@@ -2116,7 +2116,7 @@ out: 
	return ret;

}



static int format_check(struct drm_mode_fb_cmd2 *r)

static int format_check(const struct drm_mode_fb_cmd2 *r)

{

	uint32_t format = r->pixel_format & ~DRM_FORMAT_BIG_ENDIAN;
@@ -2185,7 +2185,7 @@ static int format_check(struct drm_mode_fb_cmd2 *r) 
	}

}



static int framebuffer_check(struct drm_mode_fb_cmd2 *r)

static int framebuffer_check(const struct drm_mode_fb_cmd2 *r)

{

	int ret, hsub, vsub, num_planes, i;
@@ -3126,7 +3126,7 @@ int drm_mode_connector_update_edid_property(struct drm_connector *connector, 
EXPORT_SYMBOL(drm_mode_connector_update_edid_property);



static bool drm_property_change_is_valid(struct drm_property *property,

					 __u64 value)

					 uint64_t value)

{

	if (property->flags & DRM_MODE_PROP_IMMUTABLE)

		return false;
@@ -3136,7 +3136,7 @@ static bool drm_property_change_is_valid(struct drm_property *property, 
		return true;

	} else if (property->flags & DRM_MODE_PROP_BITMASK) {

		int i;

		__u64 valid_mask = 0;

		uint64_t valid_mask = 0;

		for (i = 0; i < property->num_values; i++)

			valid_mask |= (1ULL << property->values[i]);

		return !(value & ~valid_mask);

drivers/gpu/drm/drm_edid.c

+18 −4
Original line number Diff line number Diff line
@@ -66,6 +66,8 @@ 
#define EDID_QUIRK_FIRST_DETAILED_PREFERRED	(1 << 5)

/* use +hsync +vsync for detailed mode */

#define EDID_QUIRK_DETAILED_SYNC_PP		(1 << 6)

/* Force reduced-blanking timings for detailed modes */

#define EDID_QUIRK_FORCE_REDUCED_BLANKING	(1 << 7)



struct detailed_mode_closure {

	struct drm_connector *connector;
@@ -120,6 +122,9 @@ static struct edid_quirk { 
	/* Samsung SyncMaster 22[5-6]BW */

	{ "SAM", 596, EDID_QUIRK_PREFER_LARGE_60 },

	{ "SAM", 638, EDID_QUIRK_PREFER_LARGE_60 },



	/* ViewSonic VA2026w */

	{ "VSC", 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING },

};



/*** DDC fetch and block validation ***/
@@ -885,11 +890,18 @@ static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev, 
				"Wrong Hsync/Vsync pulse width\n");

		return NULL;

	}

	mode = drm_mode_create(dev);



	if (quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) {

		mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false);

		if (!mode)

			return NULL;



	mode->type = DRM_MODE_TYPE_DRIVER;

		goto set_size;

	}



	mode = drm_mode_create(dev);

	if (!mode)

		return NULL;



	if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH)

		timing->pixel_clock = cpu_to_le16(1088);
@@ -914,8 +926,6 @@ static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev, 


	drm_mode_do_interlace_quirk(mode, pt);



	drm_mode_set_name(mode);



	if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) {

		pt->misc |= DRM_EDID_PT_HSYNC_POSITIVE | DRM_EDID_PT_VSYNC_POSITIVE;

	}
@@ -925,6 +935,7 @@ static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev, 
	mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ?

		DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;



set_size:

	mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4;

	mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8;
@@ -938,6 +949,9 @@ static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev, 
		mode->height_mm = edid->height_cm * 10;

	}



	mode->type = DRM_MODE_TYPE_DRIVER;

	drm_mode_set_name(mode);



	return mode;

}

drivers/gpu/drm/i915/i915_debugfs.c

+2 −0
Original line number Diff line number Diff line
@@ -2032,6 +2032,8 @@ void i915_debugfs_cleanup(struct drm_minor *minor) 
				 1, minor);

	drm_debugfs_remove_files((struct drm_info_list *) &i915_ring_stop_fops,

				 1, minor);

	drm_debugfs_remove_files((struct drm_info_list *) &i915_error_state_fops,

				 1, minor);

}



#endif /* CONFIG_DEBUG_FS */

drivers/gpu/drm/i915/i915_gem.c

+11 −5
Original line number Diff line number Diff line
@@ -2063,10 +2063,8 @@ i915_gem_object_unbind(struct drm_i915_gem_object *obj) 
	if (obj->gtt_space == NULL)

		return 0;



	if (obj->pin_count != 0) {

		DRM_ERROR("Attempting to unbind pinned buffer\n");

		return -EINVAL;

	}

	if (obj->pin_count)

		return -EBUSY;



	ret = i915_gem_object_finish_gpu(obj);

	if (ret)
@@ -3293,6 +3291,7 @@ struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, 
	struct drm_i915_private *dev_priv = dev->dev_private;

	struct drm_i915_gem_object *obj;

	struct address_space *mapping;

	u32 mask;



	obj = kzalloc(sizeof(*obj), GFP_KERNEL);

	if (obj == NULL)
@@ -3303,8 +3302,15 @@ struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, 
		return NULL;

	}



	mask = GFP_HIGHUSER | __GFP_RECLAIMABLE;

	if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) {

		/* 965gm cannot relocate objects above 4GiB. */

		mask &= ~__GFP_HIGHMEM;

		mask |= __GFP_DMA32;

	}



	mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;

	mapping_set_gfp_mask(mapping, GFP_HIGHUSER | __GFP_RECLAIMABLE);

	mapping_set_gfp_mask(mapping, mask);



	i915_gem_info_add_obj(dev_priv, size);

drivers/gpu/drm/i915/i915_irq.c

+7 −30
Original line number Diff line number Diff line
@@ -350,8 +350,8 @@ static void gen6_pm_rps_work(struct work_struct *work) 
{

	drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,

						    rps_work);

	u8 new_delay = dev_priv->cur_delay;

	u32 pm_iir, pm_imr;

	u8 new_delay;



	spin_lock_irq(&dev_priv->rps_lock);

	pm_iir = dev_priv->pm_iir;
@@ -360,41 +360,18 @@ static void gen6_pm_rps_work(struct work_struct *work) 
	I915_WRITE(GEN6_PMIMR, 0);

	spin_unlock_irq(&dev_priv->rps_lock);



	if (!pm_iir)

	if ((pm_iir & GEN6_PM_DEFERRED_EVENTS) == 0)

		return;



	mutex_lock(&dev_priv->dev->struct_mutex);

	if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {

		if (dev_priv->cur_delay != dev_priv->max_delay)



	if (pm_iir & GEN6_PM_RP_UP_THRESHOLD)

		new_delay = dev_priv->cur_delay + 1;

		if (new_delay > dev_priv->max_delay)

			new_delay = dev_priv->max_delay;

	} else if (pm_iir & (GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT)) {

		gen6_gt_force_wake_get(dev_priv);

		if (dev_priv->cur_delay != dev_priv->min_delay)

	else

		new_delay = dev_priv->cur_delay - 1;

		if (new_delay < dev_priv->min_delay) {

			new_delay = dev_priv->min_delay;

			I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,

				   I915_READ(GEN6_RP_INTERRUPT_LIMITS) |

				   ((new_delay << 16) & 0x3f0000));

		} else {

			/* Make sure we continue to get down interrupts

			 * until we hit the minimum frequency */

			I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,

				   I915_READ(GEN6_RP_INTERRUPT_LIMITS) & ~0x3f0000);

		}

		gen6_gt_force_wake_put(dev_priv);

	}



	gen6_set_rps(dev_priv->dev, new_delay);

	dev_priv->cur_delay = new_delay;



	/*

	 * rps_lock not held here because clearing is non-destructive. There is

	 * an *extremely* unlikely race with gen6_rps_enable() that is prevented

	 * by holding struct_mutex for the duration of the write.

	 */

	mutex_unlock(&dev_priv->dev->struct_mutex);

}

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