Commit 6ba3d706 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'pinctrl-v5.6-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl 

Pull pin control updates from Linus Walleij:
 "This is the bulk of pin control changes, nothing too exciting about
  this.

  Some changes hit arch/sh and arch/arm but are well isolated and
  acknowledged by the respective arch maintainers.

  Core changes:

   - Dropped the chained IRQ setup callback into GPIOLIB as we got rid
     of the last users of that in this changeset.

  New drivers:

   - New driver for Ingenic X1830.

   - New driver for Freescale i.MX8MP.

  Driver enhancements:

   - Fix all remaining Intel drivers to pass their IRQ chips along with
     the GPIO chips.

   - Intel Baytrail allocates its irqchip dynamically.

   - Intel Lynxpoint is thoroughly rewritten and modernized.

   - Aspeed AST2600 pin muxing and configuration is much improved.

   - Qualcomm SC7180 functions are updated and wakeup interrupt map is
     provided.

   - A whole slew of Renesas SH-PFC cleanups and improvements.

   - Fix up the Intel DT bindings to use the generic YAML DT bindings
     schema (a first user of this)"

* tag 'pinctrl-v5.6-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (99 commits)
  pinctrl: madera: Remove extra blank line
  pinctrl: qcom: Don't lock around irq_set_irq_wake()
  pinctrl: mvebu: armada-37xx: use use platform api
  gpio: Drop the chained IRQ handler assign function
  pinctrl: freescale: Add i.MX8MP pinctrl driver support
  dt-bindings: imx: Add pinctrl binding doc for i.MX8MP
  pinctrl: tigerlake: Tiger Lake uses _HID enumeration
  pinctrl: sunrisepoint: Add Coffee Lake-S ACPI ID
  pinctrl: iproc: Use platform_get_irq_optional() to avoid error message
  pinctrl: dt-bindings: Fix some errors in the lgm and pinmux schema
  pinctrl: intel: Pass irqchip when adding gpiochip
  pinctrl: intel: Add GPIO <-> pin mapping ranges via callback
  pinctrl: baytrail: Replace WARN with dev_info_once when setting direct-irq pin to output
  pinctrl: baytrail: Do not clear IRQ flags on direct-irq enabled pins
  pinctrl: sunrisepoint: Add missing Interrupt Status register offset
  pinctrl: sh-pfc: Split R-Car H3 support in two independent drivers
  pinctrl: artpec6: fix __iomem on reg in set
  pinctrl: ingenic: Use devm_platform_ioremap_resource()
  pinctrl: ingenic: Factorize irq_set_type function
  pinctrl: ingenic: Remove duplicated ingenic_chip_info structures
  ...
parents fa889d85 122ce22c

Documentation/devicetree/bindings/pinctrl/aspeed,ast2600-pinctrl.yaml

+5 −4
Original line number Diff line number Diff line
@@ -54,8 +54,9 @@ patternProperties: 
              TACH10, TACH11, TACH12, TACH13, TACH14, TACH15, TACH2, TACH3,

              TACH4, TACH5, TACH6, TACH7, TACH8, TACH9, THRU0, THRU1, THRU2,

              THRU3, TXD1, TXD2, TXD3, TXD4, UART10, UART11, UART12, UART13,

              UART6, UART7, UART8, UART9, VB, VGAHS, VGAVS, WDTRST1, WDTRST2,

              WDTRST3, WDTRST4, ]

              UART6, UART7, UART8, UART9, USBAD, USBADP, USB2AH, USB2AHP,

              USB2BD, USB2BH, VB, VGAHS, VGAVS, WDTRST1, WDTRST2, WDTRST3,

              WDTRST4, ]

        groups:

          allOf:

            - $ref: "/schemas/types.yaml#/definitions/string"
@@ -85,8 +86,8 @@ patternProperties: 
              TACH10, TACH11, TACH12, TACH13, TACH14, TACH15, TACH2, TACH3,

              TACH4, TACH5, TACH6, TACH7, TACH8, TACH9, THRU0, THRU1, THRU2,

              THRU3, TXD1, TXD2, TXD3, TXD4, UART10, UART11, UART12G0,

              UART12G1, UART13G0, UART13G1, UART6, UART7, UART8, UART9, VB,

              VGAHS, VGAVS, WDTRST1, WDTRST2, WDTRST3, WDTRST4, ]

              UART12G1, UART13G0, UART13G1, UART6, UART7, UART8, UART9, USBA,

              USBB, VB, VGAHS, VGAVS, WDTRST1, WDTRST2, WDTRST3, WDTRST4, ]



required:

  - compatible

Documentation/devicetree/bindings/pinctrl/fsl,imx8mp-pinctrl.yaml

0 → 100644
+69 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: GPL-2.0

%YAML 1.2

---

$id: http://devicetree.org/schemas/pinctrl/fsl,imx8mp-pinctrl.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Freescale IMX8MP IOMUX Controller



maintainers:

  - Anson Huang <Anson.Huang@nxp.com>



description:

  Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory

  for common binding part and usage.



properties:

  compatible:

    const: fsl,imx8mp-iomuxc



  reg:

    maxItems: 1



# Client device subnode's properties

patternProperties:

  'grp$':

    type: object

    description:

      Pinctrl node's client devices use subnodes for desired pin configuration.

      Client device subnodes use below standard properties.



    properties:

      fsl,pins:

        allOf:

          - $ref: /schemas/types.yaml#/definitions/uint32-array

        description:

          each entry consists of 6 integers and represents the mux and config

          setting for one pin. The first 5 integers <mux_reg conf_reg input_reg

          mux_val input_val> are specified using a PIN_FUNC_ID macro, which can

          be found in <arch/arm64/boot/dts/freescale/imx8mp-pinfunc.h>. The last

          integer CONFIG is the pad setting value like pull-up on this pin. Please

          refer to i.MX8M Plus Reference Manual for detailed CONFIG settings.



    required:

      - fsl,pins



    additionalProperties: false



required:

  - compatible

  - reg



additionalProperties: false



examples:

  # Pinmux controller node

  - |

    iomuxc: pinctrl@30330000 {

        compatible = "fsl,imx8mp-iomuxc";

        reg = <0x30330000 0x10000>;



        pinctrl_uart2: uart2grp {

            fsl,pins = <

                0x228 0x488 0x5F0 0x0 0x6	0x49

                0x228 0x488 0x000 0x0 0x0	0x49

            >;

        };

    };



...

Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.txt

+5 −3
Original line number Diff line number Diff line
@@ -10,9 +10,9 @@ GPIO port configuration registers and it is typical to refer to pins using the 
naming scheme "PxN" where x is a character identifying the GPIO port with

which the pin is associated and N is an integer from 0 to 31 identifying the

pin within that GPIO port. For example PA0 is the first pin in GPIO port A, and

PB31 is the last pin in GPIO port B. The jz4740 and the x1000 contains 4 GPIO

ports, PA to PD, for a total of 128 pins. The jz4760, the jz4770 and the jz4780

contains 6 GPIO ports, PA to PF, for a total of 192 pins.

PB31 is the last pin in GPIO port B. The jz4740, the x1000 and the x1830

contains 4 GPIO ports, PA to PD, for a total of 128 pins. The jz4760, the

jz4770 and the jz4780 contains 6 GPIO ports, PA to PF, for a total of 192 pins.





Required properties:
@@ -28,6 +28,7 @@ Required properties: 
    - "ingenic,x1000-pinctrl"

    - "ingenic,x1000e-pinctrl"

    - "ingenic,x1500-pinctrl"

    - "ingenic,x1830-pinctrl"

 - reg: Address range of the pinctrl registers.
@@ -40,6 +41,7 @@ Required properties for sub-nodes (GPIO chips): 
    - "ingenic,jz4770-gpio"

    - "ingenic,jz4780-gpio"

    - "ingenic,x1000-gpio"

    - "ingenic,x1830-gpio"

 - reg: The GPIO bank number.

 - interrupt-controller: Marks the device node as an interrupt controller.

 - interrupts: Interrupt specifier for the controllers interrupt.

Documentation/devicetree/bindings/pinctrl/intel,lgm-pinctrl.yaml→Documentation/devicetree/bindings/pinctrl/intel,lgm-io.yaml

+75 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/bindings/pinctrl/intel,lgm-pinctrl.yaml#

$id: http://devicetree.org/schemas/pinctrl/intel,lgm-io.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Intel Lightning Mountain SoC pinmux & GPIO controller binding
@@ -13,11 +13,6 @@ description: | 
  Pinmux & GPIO controller controls pin multiplexing & configuration including

  GPIO function selection & GPIO attributes configuration.



  Please refer to [1] for details of the common pinctrl bindings used by the

  client devices.



  [1] Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt



properties:

  compatible:

    const: intel,lgm-io
@@ -29,60 +24,24 @@ properties: 
patternProperties:

  '-pins$':

    type: object

    allOf:

      - $ref: pincfg-node.yaml#

      - $ref: pinmux-node.yaml#

    description:

      Pinctrl node's client devices use subnodes for desired pin configuration.

      Client device subnodes use below standard properties.



    properties:

      function:

        $ref: /schemas/types.yaml#/definitions/string

        description:

          A string containing the name of the function to mux to the group.



      groups:

        $ref: /schemas/types.yaml#/definitions/string-array

        description:

          An array of strings identifying the list of groups.



      pins:

        $ref: /schemas/types.yaml#/definitions/uint32-array

        description:

          List of pins to select with this function.



      pinmux:

        description: The applicable mux group.

        allOf:

          - $ref: "/schemas/types.yaml#/definitions/uint32-array"



      bias-pull-up:

        type: boolean



      bias-pull-down:

        type: boolean



      drive-strength:

        description: |

          Selects the drive strength for the specified pins in mA.

          0: 2 mA

          1: 4 mA

          2: 8 mA

          3: 12 mA

        allOf:

          - $ref: /schemas/types.yaml#/definitions/uint32

          - enum: [0, 1, 2, 3]



      slew-rate:

        type: boolean

        description: |

          Sets slew rate for specified pins.

          0: slow slew

          1: fast slew



      drive-open-drain:

        type: boolean



      output-enable:

        type: boolean

      function: true

      groups: true

      pins: true

      pinmux: true

      bias-pull-up: true

      bias-pull-down: true

      drive-strength: true

      slew-rate: true

      drive-open-drain: true

      output-enable: true



    required:

      - function
@@ -100,7 +59,7 @@ examples: 
  # Pinmux controller node

  - |

    pinctrl: pinctrl@e2880000 {

        compatible = "intel,lgm-pinctrl";

        compatible = "intel,lgm-io";

        reg = <0xe2880000 0x100000>;



        uart0-pins {

Documentation/devicetree/bindings/pinctrl/pinmux-node.yaml

+1 −1
Original line number Diff line number Diff line
@@ -114,7 +114,7 @@ properties: 
      specific binding for the hardware defines whether the entries are integers

      or strings, and their meaning.



  group:

  groups:

    $ref: /schemas/types.yaml#/definitions/string-array

    description:

      the group to apply the properties to, if the driver supports

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