Commit 6b8e1eb7 authored by Eric Bernstein's avatar Eric Bernstein Committed by Alex Deucher
Browse files

drm/amd/display: Update HW sequencer initialization 



Signed-off-by: default avatarEric Bernstein <eric.bernstein@amd.com>
Reviewed-by: default avatarTony Cheng <Tony.Cheng@amd.com>
Acked-by: default avatarHarry Wentland <harry.wentland@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 3ba43a59

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

+3 −3
Original line number Diff line number Diff line
@@ -849,7 +849,7 @@ static void dcn10_verify_allow_pstate_change_high(struct dc *dc) 
}



/* trigger HW to start disconnect plane from stream on the next vsync */

static void plane_atomic_disconnect(struct dc *dc, struct pipe_ctx *pipe_ctx)

void hwss1_plane_atomic_disconnect(struct dc *dc, struct pipe_ctx *pipe_ctx)

{

	struct hubp *hubp = pipe_ctx->plane_res.hubp;

	int dpp_id = pipe_ctx->plane_res.dpp->inst;
@@ -1032,7 +1032,7 @@ static void dcn10_init_hw(struct dc *dc) 
		dc->res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true;

		pipe_ctx->stream_res.opp = dc->res_pool->opps[i];



		plane_atomic_disconnect(dc, pipe_ctx);

		hwss1_plane_atomic_disconnect(dc, pipe_ctx);

	}



	for (i = 0; i < dc->res_pool->pipe_count; i++) {
@@ -2267,7 +2267,7 @@ static void dcn10_apply_ctx_for_surface( 
			old_pipe_ctx->plane_state &&

			old_pipe_ctx->stream_res.tg == tg) {



			plane_atomic_disconnect(dc, old_pipe_ctx);

			hwss1_plane_atomic_disconnect(dc, old_pipe_ctx);

			removed_pipe[i] = true;



			DC_LOG_DC(

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h

+2 −0
Original line number Diff line number Diff line
@@ -37,4 +37,6 @@ extern void fill_display_configs( 


bool is_rgb_cspace(enum dc_color_space output_color_space);



void hwss1_plane_atomic_disconnect(struct dc *dc, struct pipe_ctx *pipe_ctx);



#endif /* __DC_HWSS_DCN10_H__ */

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c

+5 −5
Original line number Diff line number Diff line
@@ -360,7 +360,7 @@ void optc1_program_timing( 


}



static void optc1_set_blank_data_double_buffer(struct timing_generator *optc, bool enable)

void optc1_set_blank_data_double_buffer(struct timing_generator *optc, bool enable)

{

	struct optc *optc1 = DCN10TG_FROM_TG(optc);
@@ -1257,20 +1257,20 @@ void optc1_read_otg_state(struct optc *optc1, 
			OPTC_UNDERFLOW_OCCURRED_STATUS, &s->underflow_occurred_status);

}



static void optc1_clear_optc_underflow(struct timing_generator *optc)

void optc1_clear_optc_underflow(struct timing_generator *optc)

{

	struct optc *optc1 = DCN10TG_FROM_TG(optc);



	REG_UPDATE(OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_CLEAR, 1);

}



static void optc1_tg_init(struct timing_generator *optc)

void optc1_tg_init(struct timing_generator *optc)

{

	optc1_set_blank_data_double_buffer(optc, true);

	optc1_clear_optc_underflow(optc);

}



static bool optc1_is_tg_enabled(struct timing_generator *optc)

bool optc1_is_tg_enabled(struct timing_generator *optc)

{

	struct optc *optc1 = DCN10TG_FROM_TG(optc);

	uint32_t otg_enabled = 0;
@@ -1281,7 +1281,7 @@ static bool optc1_is_tg_enabled(struct timing_generator *optc) 


}



static bool optc1_is_optc_underflow_occurred(struct timing_generator *optc)

bool optc1_is_optc_underflow_occurred(struct timing_generator *optc)

{

	struct optc *optc1 = DCN10TG_FROM_TG(optc);

	uint32_t underflow_occurred = 0;

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h

+10 −0
Original line number Diff line number Diff line
@@ -497,4 +497,14 @@ void optc1_program_stereo(struct timing_generator *optc, 


bool optc1_is_stereo_left_eye(struct timing_generator *optc);



void optc1_clear_optc_underflow(struct timing_generator *optc);



void optc1_tg_init(struct timing_generator *optc);



bool optc1_is_tg_enabled(struct timing_generator *optc);



bool optc1_is_optc_underflow_occurred(struct timing_generator *optc);



void optc1_set_blank_data_double_buffer(struct timing_generator *optc, bool enable);



#endif /* __DC_TIMING_GENERATOR_DCN10_H__ */

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