Commit 6b8a5eeb authored by Eugeni Dodonov's avatar Eugeni Dodonov Committed by Daniel Vetter
Browse files

drm/i915: define Haswell watermarks and clock gating 



For now, we simple reuse the Ivy Bridge routines here.

Signed-off-by: default avatarEugeni Dodonov <eugeni.dodonov@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 4abb3c8c

drivers/gpu/drm/i915/intel_pm.c

+11 −0
Original line number Diff line number Diff line
@@ -3685,6 +3685,17 @@ void intel_init_pm(struct drm_device *dev) 
			}

			dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;

			dev_priv->display.sanitize_pm = gen6_sanitize_pm;

		} else if (IS_HASWELL(dev)) {

			if (SNB_READ_WM0_LATENCY()) {

				dev_priv->display.update_wm = sandybridge_update_wm;

				dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;

			} else {

				DRM_DEBUG_KMS("Failed to read display plane latency. "

					      "Disable CxSR\n");

				dev_priv->display.update_wm = NULL;

			}

			dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;

			dev_priv->display.sanitize_pm = gen6_sanitize_pm;

		} else

			dev_priv->display.update_wm = NULL;

	} else if (IS_VALLEYVIEW(dev)) {

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