Commit 6b71acec authored Jan 19, 2018 by Jerome Brunet

clk: meson: axg: add the fractional part of the fixed_pll



The fixed_pll also has a fractional part. On axg s400 board, without
this parameter, the calculated rate is off by ~8Mhz (0,4%). The fixed_pll
being the root of the peripheral clock tree, this error is propagated to
the rest of the clocks

Adding the definition of the parameter fixes the problem

Fixes: 78b4af31 ("clk: meson-axg: add clock controller drivers")
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>

parent 07f45e2e

drivers/clk/meson/axg.c

+5 −0

Original line number	Diff line number	Diff line
		@@ -37,6 +37,11 @@ static struct meson_clk_pll axg_fixed_pll = {
		.shift = 16,
		.width = 2,
		},
		.frac = {
		.reg_off = HHI_MPLL_CNTL2,
		.shift = 0,
		.width = 12,
		},
		.lock = &meson_clk_lock,
		.hw.init = &(struct clk_init_data){
		.name = "fixed_pll",

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