iommu/mediatek: Use a u32 flags to describe different HW features (6b717796) · Commits · 戴 / test

drivers/iommu/mtk_iommu.c

+17 −11

Original line number	Diff line number	Diff line
		@@ -100,6 +100,15 @@
		#define MTK_M4U_TO_LARB(id) (((id) >> 5) & 0xf)
		#define MTK_M4U_TO_PORT(id) ((id) & 0x1f)

		#define HAS_4GB_MODE BIT(0)
		/* HW will use the EMI clock if there isn't the "bclk". */
		#define HAS_BCLK BIT(1)
		#define HAS_VLD_PA_RNG BIT(2)
		#define RESET_AXI BIT(3)

		#define MTK_IOMMU_HAS_FLAG(pdata, _x) \
		((((pdata)->flags) & (_x)) == (_x))

		struct mtk_iommu_domain {
		struct io_pgtable_cfg cfg;
		struct io_pgtable_ops *iop;
		@@ -563,7 +572,8 @@ static int mtk_iommu_hw_init(const struct mtk_iommu_data *data)
		upper_32_bits(data->protect_base);
		writel_relaxed(regval, data->base + REG_MMU_IVRP_PADDR);

		if (data->enable_4GB && data->plat_data->has_vld_pa_rng) {
		if (data->enable_4GB &&
		MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_VLD_PA_RNG)) {
		/*
		* If 4GB mode is enabled, the validate PA range is from
		* 0x1_0000_0000 to 0x1_ffff_ffff. here record bit[32:30].
		@@ -573,7 +583,7 @@ static int mtk_iommu_hw_init(const struct mtk_iommu_data *data)
		}
		writel_relaxed(0, data->base + REG_MMU_DCM_DIS);

		if (data->plat_data->reset_axi) {
		if (MTK_IOMMU_HAS_FLAG(data->plat_data, RESET_AXI)) {
		/* The register is called STANDARD_AXI_MODE in this case */
		writel_relaxed(0, data->base + REG_MMU_MISC_CTRL);
		}
		@@ -618,7 +628,7 @@ static int mtk_iommu_probe(struct platform_device *pdev)

		/* Whether the current dram is over 4GB */
		data->enable_4GB = !!(max_pfn > (BIT_ULL(32) >> PAGE_SHIFT));
		if (!data->plat_data->has_4gb_mode)
		if (!MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_4GB_MODE))
		data->enable_4GB = false;

		res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
		@@ -631,7 +641,7 @@ static int mtk_iommu_probe(struct platform_device *pdev)
		if (data->irq < 0)
		return data->irq;

		if (data->plat_data->has_bclk) {
		if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_BCLK)) {
		data->bclk = devm_clk_get(dev, "bclk");
		if (IS_ERR(data->bclk))
		return PTR_ERR(data->bclk);
		@@ -763,23 +773,19 @@ static const struct dev_pm_ops mtk_iommu_pm_ops = {

		static const struct mtk_iommu_plat_data mt2712_data = {
		.m4u_plat = M4U_MT2712,
		.has_4gb_mode = true,
		.has_bclk = true,
		.has_vld_pa_rng = true,
		.flags = HAS_4GB_MODE \| HAS_BCLK \| HAS_VLD_PA_RNG,
		.larbid_remap = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9},
		};

		static const struct mtk_iommu_plat_data mt8173_data = {
		.m4u_plat = M4U_MT8173,
		.has_4gb_mode = true,
		.has_bclk = true,
		.reset_axi = true,
		.flags = HAS_4GB_MODE \| HAS_BCLK \| RESET_AXI,
		.larbid_remap = {0, 1, 2, 3, 4, 5}, /* Linear mapping. */
		};

		static const struct mtk_iommu_plat_data mt8183_data = {
		.m4u_plat = M4U_MT8183,
		.reset_axi = true,
		.flags = RESET_AXI,
		.larbid_remap = {0, 4, 5, 6, 7, 2, 3, 1},
		};

drivers/iommu/mtk_iommu.h

+1 −6

Original line number	Diff line number	Diff line
		@@ -39,12 +39,7 @@ enum mtk_iommu_plat {

		struct mtk_iommu_plat_data {
		enum mtk_iommu_plat m4u_plat;
		bool has_4gb_mode;

		/* HW will use the EMI clock if there isn't the "bclk". */
		bool has_bclk;
		bool has_vld_pa_rng;
		bool reset_axi;
		u32 flags;
		unsigned char larbid_remap[MTK_LARB_NR_MAX];
		};

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