Commit 6b0b594b authored by Timur Tabi's avatar Timur Tabi Committed by Kumar Gala
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[POWERPC] qe: miscellaneous code improvements and fixes to the QE library 



This patch makes numerous miscellaneous code improvements to the QE library.

1. Remove struct ucc_common and merge ucc_init_guemr() into ucc_set_type()
   (every caller of ucc_init_guemr() also calls ucc_set_type()).  Modify all
   callers of ucc_set_type() accordingly.

2. Remove the unused enum ucc_pram_initial_offset.

3. Refactor qe_setbrg(), also implement work-around for errata QE_General4.

4. Several printk() calls were missing the terminating \n.

5. Add __iomem where needed, and change u16 to __be16 and u32 to __be32 where
   appropriate.

6. In ucc_slow_init() the RBASE and TBASE registers in the PRAM were programmed
   with the wrong value.

7. Add the protocol type to struct us_info and updated ucc_slow_init() to
   use it, instead of always programming QE_CR_PROTOCOL_UNSPECIFIED.

8. Rename ucc_slow_restart_x() to ucc_slow_restart_tx()

9. Add several macros in qe.h (mostly for slow UCC support, but also to
   standardize some naming convention) and remove several unused macros.

10. Update ucc_geth.c to use the new macros.

11. Add ucc_slow_info.protocol to specify which QE_CR_PROTOCOL_xxx protcol
    to use when initializing the UCC in ucc_slow_init().

12. Rename ucc_slow_pram.rfcr to rbmr and ucc_slow_pram.tfcr to tbmr, since
    these are the real names of the registers.

13. Use the setbits, clrbits, and clrsetbits where appropriate.

14. Refactor ucc_set_qe_mux_rxtx().

15. Remove all instances of 'volatile'.

16. Simplify get_cmxucr_reg();

17. Replace qe_mux.cmxucrX with qe_mux.cmxucr[].

18. Updated struct ucc_geth because struct ucc_fast is not padded any more.

Signed-off-by: default avatarTimur Tabi <timur@freescale.com>
Signed-off-by: default avatarKumar Gala <galak@kernel.crashing.org>
parent 60396807

arch/powerpc/sysdev/qe_lib/qe.c

+23 −13
Original line number Diff line number Diff line
@@ -141,7 +141,7 @@ EXPORT_SYMBOL(qe_issue_cmd); 
 * 16 BRGs, which can be connected to the QE channels or output

 * as clocks. The BRGs are in two different block of internal

 * memory mapped space.

 * The baud rate clock is the system clock divided by something.

 * The BRG clock is the QE clock divided by 2.

 * It was set up long ago during the initial boot phase and is

 * is given to us.

 * Baud rate clocks are zero-based in the driver code (as that maps
@@ -165,28 +165,38 @@ unsigned int get_brg_clk(void) 
	return brg_clk;

}



/* This function is used by UARTS, or anything else that uses a 16x

 * oversampled clock.

/* Program the BRG to the given sampling rate and multiplier

 *

 * @brg: the BRG, 1-16

 * @rate: the desired sampling rate

 * @multiplier: corresponds to the value programmed in GUMR_L[RDCR] or

 * GUMR_L[TDCR].  E.g., if this BRG is the RX clock, and GUMR_L[RDCR]=01,

 * then 'multiplier' should be 8.

 *

 * Also note that the value programmed into the BRGC register must be even.

 */

void qe_setbrg(u32 brg, u32 rate)

void qe_setbrg(unsigned int brg, unsigned int rate, unsigned int multiplier)

{

	volatile u32 *bp;

	u32 divisor, tempval;

	int div16 = 0;

	u32 div16 = 0;



	bp = &qe_immr->brg.brgc[brg];

	divisor = get_brg_clk() / (rate * multiplier);



	divisor = (get_brg_clk() / rate);

	if (divisor > QE_BRGC_DIVISOR_MAX + 1) {

		div16 = 1;

		div16 = QE_BRGC_DIV16;

		divisor /= 16;

	}



	tempval = ((divisor - 1) << QE_BRGC_DIVISOR_SHIFT) | QE_BRGC_ENABLE;

	if (div16)

		tempval |= QE_BRGC_DIV16;

	/* Errata QE_General4, which affects some MPC832x and MPC836x SOCs, says

	   that the BRG divisor must be even if you're not using divide-by-16

	   mode. */

	if (!div16 && (divisor & 1))

		divisor++;



	tempval = ((divisor - 1) << QE_BRGC_DIVISOR_SHIFT) |

		QE_BRGC_ENABLE | div16;



	out_be32(bp, tempval);

	out_be32(&qe_immr->brg.brgc[brg - 1], tempval);

}



/* Initialize SNUMs (thread serial numbers) according to

arch/powerpc/sysdev/qe_lib/qe_ic.c

+0 −2
Original line number Diff line number Diff line
@@ -405,8 +405,6 @@ void __init qe_ic_init(struct device_node *node, unsigned int flags) 
		set_irq_data(qe_ic->virq_high, qe_ic);

		set_irq_chained_handler(qe_ic->virq_high, qe_ic_cascade_high);

	}



	printk("QEIC (%d IRQ sources) at %p\n", NR_QE_IC_INTS, qe_ic->regs);

}



void qe_ic_set_highest_priority(unsigned int virq, int high)

arch/powerpc/sysdev/qe_lib/qe_io.c

+14 −21
Original line number Diff line number Diff line
@@ -195,28 +195,21 @@ EXPORT_SYMBOL(par_io_of_config); 
#ifdef DEBUG

static void dump_par_io(void)

{

	int i;

	unsigned int i;



	printk(KERN_INFO "PAR IO registars:\n");

	printk(KERN_INFO "Base address: 0x%08x\n", (u32) par_io);

	printk(KERN_INFO "%s: par_io=%p\n", __FUNCTION__, par_io);

	for (i = 0; i < num_par_io_ports; i++) {

		printk(KERN_INFO "cpodr[%d] : addr - 0x%08x, val - 0x%08x\n",

		       i, (u32) & par_io[i].cpodr,

		printk(KERN_INFO "	cpodr[%u]=%08x\n", i,

			in_be32(&par_io[i].cpodr));

		printk(KERN_INFO "cpdata[%d]: addr - 0x%08x, val - 0x%08x\n",

		       i, (u32) & par_io[i].cpdata,

		printk(KERN_INFO "	cpdata[%u]=%08x\n", i,

			in_be32(&par_io[i].cpdata));

		printk(KERN_INFO "cpdir1[%d]: addr - 0x%08x, val - 0x%08x\n",

		       i, (u32) & par_io[i].cpdir1,

		printk(KERN_INFO "	cpdir1[%u]=%08x\n", i,

			in_be32(&par_io[i].cpdir1));

		printk(KERN_INFO "cpdir2[%d]: addr - 0x%08x, val - 0x%08x\n",

		       i, (u32) & par_io[i].cpdir2,

		printk(KERN_INFO "	cpdir2[%u]=%08x\n", i,

			in_be32(&par_io[i].cpdir2));

		printk(KERN_INFO "cppar1[%d]: addr - 0x%08x, val - 0x%08x\n",

		       i, (u32) & par_io[i].cppar1,

		printk(KERN_INFO "	cppar1[%u]=%08x\n", i,

			in_be32(&par_io[i].cppar1));

		printk(KERN_INFO "cppar2[%d]: addr - 0x%08x, val - 0x%08x\n",

		       i, (u32) & par_io[i].cppar2,

		printk(KERN_INFO "	cppar2[%u]=%08x\n", i,

			in_be32(&par_io[i].cppar2));

	}

arch/powerpc/sysdev/qe_lib/ucc.c

+115 −155
Original line number Diff line number Diff line
@@ -28,228 +28,188 @@ 


static DEFINE_SPINLOCK(ucc_lock);



int ucc_set_qe_mux_mii_mng(int ucc_num)

int ucc_set_qe_mux_mii_mng(unsigned int ucc_num)

{

	unsigned long flags;



	if (ucc_num > UCC_MAX_NUM - 1)

		return -EINVAL;



	spin_lock_irqsave(&ucc_lock, flags);

	out_be32(&qe_immr->qmx.cmxgcr,

		 ((in_be32(&qe_immr->qmx.cmxgcr) &

		   ~QE_CMXGCR_MII_ENET_MNG) |

		  (ucc_num << QE_CMXGCR_MII_ENET_MNG_SHIFT)));

	clrsetbits_be32(&qe_immr->qmx.cmxgcr, QE_CMXGCR_MII_ENET_MNG,

		ucc_num << QE_CMXGCR_MII_ENET_MNG_SHIFT);

	spin_unlock_irqrestore(&ucc_lock, flags);



	return 0;

}

EXPORT_SYMBOL(ucc_set_qe_mux_mii_mng);



int ucc_set_type(int ucc_num, struct ucc_common *regs,

		 enum ucc_speed_type speed)

{

	u8 guemr = 0;



	/* check if the UCC number is in range. */

	if ((ucc_num > UCC_MAX_NUM - 1) || (ucc_num < 0))

		return -EINVAL;



	guemr = regs->guemr;

	guemr &= ~(UCC_GUEMR_MODE_MASK_RX | UCC_GUEMR_MODE_MASK_TX);

	switch (speed) {

	case UCC_SPEED_TYPE_SLOW:

		guemr |= (UCC_GUEMR_MODE_SLOW_RX | UCC_GUEMR_MODE_SLOW_TX);

		break;

	case UCC_SPEED_TYPE_FAST:

		guemr |= (UCC_GUEMR_MODE_FAST_RX | UCC_GUEMR_MODE_FAST_TX);

		break;

	default:

		return -EINVAL;

	}

	regs->guemr = guemr;



	return 0;

}



int ucc_init_guemr(struct ucc_common *regs)

/* Configure the UCC to either Slow or Fast.

 *

 * A given UCC can be figured to support either "slow" devices (e.g. UART)

 * or "fast" devices (e.g. Ethernet).

 *

 * 'ucc_num' is the UCC number, from 0 - 7.

 *

 * This function also sets the UCC_GUEMR_SET_RESERVED3 bit because that bit

 * must always be set to 1.

 */

int ucc_set_type(unsigned int ucc_num, enum ucc_speed_type speed)

{

	u8 guemr = 0;



	if (!regs)

		return -EINVAL;



	/* Set bit 3 (which is reserved in the GUEMR register) to 1 */

	guemr = UCC_GUEMR_SET_RESERVED3;



	regs->guemr = guemr;



	return 0;

}

	u8 __iomem *guemr;



static void get_cmxucr_reg(int ucc_num, volatile u32 ** p_cmxucr, u8 * reg_num,

			   u8 * shift)

{

	/* The GUEMR register is at the same location for both slow and fast

	   devices, so we just use uccX.slow.guemr. */

	switch (ucc_num) {

	case 0: *p_cmxucr = &(qe_immr->qmx.cmxucr1);

		*reg_num = 1;

		*shift = 16;

	case 0: guemr = &qe_immr->ucc1.slow.guemr;

		break;

	case 2: *p_cmxucr = &(qe_immr->qmx.cmxucr1);

		*reg_num = 1;

		*shift = 0;

	case 1: guemr = &qe_immr->ucc2.slow.guemr;

		break;

	case 4: *p_cmxucr = &(qe_immr->qmx.cmxucr2);

		*reg_num = 2;

		*shift = 16;

	case 2: guemr = &qe_immr->ucc3.slow.guemr;

		break;

	case 6: *p_cmxucr = &(qe_immr->qmx.cmxucr2);

		*reg_num = 2;

		*shift = 0;

	case 3: guemr = &qe_immr->ucc4.slow.guemr;

		break;

	case 1: *p_cmxucr = &(qe_immr->qmx.cmxucr3);

		*reg_num = 3;

		*shift = 16;

	case 4: guemr = &qe_immr->ucc5.slow.guemr;

		break;

	case 3: *p_cmxucr = &(qe_immr->qmx.cmxucr3);

		*reg_num = 3;

		*shift = 0;

	case 5: guemr = &qe_immr->ucc6.slow.guemr;

		break;

	case 5: *p_cmxucr = &(qe_immr->qmx.cmxucr4);

		*reg_num = 4;

		*shift = 16;

	case 6: guemr = &qe_immr->ucc7.slow.guemr;

		break;

	case 7: *p_cmxucr = &(qe_immr->qmx.cmxucr4);

		*reg_num = 4;

		*shift = 0;

	case 7: guemr = &qe_immr->ucc8.slow.guemr;

		break;

	default:

		break;

		return -EINVAL;

	}



	clrsetbits_8(guemr, UCC_GUEMR_MODE_MASK,

		UCC_GUEMR_SET_RESERVED3 | speed);



	return 0;

}



static void get_cmxucr_reg(unsigned int ucc_num, __be32 **cmxucr,

	unsigned int *reg_num, unsigned int *shift)

{

	unsigned int cmx = ((ucc_num & 1) << 1) + (ucc_num > 3);



	*reg_num = cmx + 1;

	*cmxucr = &qe_immr->qmx.cmxucr[cmx];

	*shift = 16 - 8 * (ucc_num & 2);

}



int ucc_mux_set_grant_tsa_bkpt(int ucc_num, int set, u32 mask)

int ucc_mux_set_grant_tsa_bkpt(unsigned int ucc_num, int set, u32 mask)

{

	volatile u32 *p_cmxucr;

	u8 reg_num;

	u8 shift;

	__be32 *cmxucr;

	unsigned int reg_num;

	unsigned int shift;



	/* check if the UCC number is in range. */

	if ((ucc_num > UCC_MAX_NUM - 1) || (ucc_num < 0))

	if (ucc_num > UCC_MAX_NUM - 1)

		return -EINVAL;



	get_cmxucr_reg(ucc_num, &p_cmxucr, &reg_num, &shift);

	get_cmxucr_reg(ucc_num, &cmxucr, &reg_num, &shift);



	if (set)

		out_be32(p_cmxucr, in_be32(p_cmxucr) | (mask << shift));

		setbits32(cmxucr, mask << shift);

	else

		out_be32(p_cmxucr, in_be32(p_cmxucr) & ~(mask << shift));

		clrbits32(cmxucr, mask << shift);



	return 0;

}



int ucc_set_qe_mux_rxtx(int ucc_num, enum qe_clock clock, enum comm_dir mode)

int ucc_set_qe_mux_rxtx(unsigned int ucc_num, enum qe_clock clock,

	enum comm_dir mode)

{

	volatile u32 *p_cmxucr;

	u8 reg_num;

	u8 shift;

	u32 clock_bits;

	u32 clock_mask;

	int source = -1;

	__be32 *cmxucr;

	unsigned int reg_num;

	unsigned int shift;

	u32 clock_bits = 0;



	/* check if the UCC number is in range. */

	if ((ucc_num > UCC_MAX_NUM - 1) || (ucc_num < 0))

	if (ucc_num > UCC_MAX_NUM - 1)

		return -EINVAL;



	if (!((mode == COMM_DIR_RX) || (mode == COMM_DIR_TX))) {

		printk(KERN_ERR

		       "ucc_set_qe_mux_rxtx: bad comm mode type passed.");

	/* The communications direction must be RX or TX */

	if (!((mode == COMM_DIR_RX) || (mode == COMM_DIR_TX)))

		return -EINVAL;

	}



	get_cmxucr_reg(ucc_num, &p_cmxucr, &reg_num, &shift);

	get_cmxucr_reg(ucc_num, &cmxucr, &reg_num, &shift);



	switch (reg_num) {

	case 1:

		switch (clock) {

		case QE_BRG1:	source = 1; break;

		case QE_BRG2:	source = 2; break;

		case QE_BRG7:	source = 3; break;

		case QE_BRG8:	source = 4; break;

		case QE_CLK9:	source = 5; break;

		case QE_CLK10:	source = 6; break;

		case QE_CLK11:	source = 7; break;

		case QE_CLK12:	source = 8; break;

		case QE_CLK15:	source = 9; break;

		case QE_CLK16:	source = 10; break;

		default: 	source = -1; break;

		case QE_BRG1:	clock_bits = 1; break;

		case QE_BRG2:	clock_bits = 2; break;

		case QE_BRG7:	clock_bits = 3; break;

		case QE_BRG8:	clock_bits = 4; break;

		case QE_CLK9:	clock_bits = 5; break;

		case QE_CLK10:	clock_bits = 6; break;

		case QE_CLK11:	clock_bits = 7; break;

		case QE_CLK12:	clock_bits = 8; break;

		case QE_CLK15:	clock_bits = 9; break;

		case QE_CLK16:	clock_bits = 10; break;

		default: break;

		}

		break;

	case 2:

		switch (clock) {

		case QE_BRG5:	source = 1; break;

		case QE_BRG6:	source = 2; break;

		case QE_BRG7:	source = 3; break;

		case QE_BRG8:	source = 4; break;

		case QE_CLK13:	source = 5; break;

		case QE_CLK14:	source = 6; break;

		case QE_CLK19:	source = 7; break;

		case QE_CLK20:	source = 8; break;

		case QE_CLK15:	source = 9; break;

		case QE_CLK16:	source = 10; break;

		default: 	source = -1; break;

		case QE_BRG5:	clock_bits = 1; break;

		case QE_BRG6:	clock_bits = 2; break;

		case QE_BRG7:	clock_bits = 3; break;

		case QE_BRG8:	clock_bits = 4; break;

		case QE_CLK13:	clock_bits = 5; break;

		case QE_CLK14:	clock_bits = 6; break;

		case QE_CLK19:	clock_bits = 7; break;

		case QE_CLK20:	clock_bits = 8; break;

		case QE_CLK15:	clock_bits = 9; break;

		case QE_CLK16:	clock_bits = 10; break;

		default: break;

		}

		break;

	case 3:

		switch (clock) {

		case QE_BRG9:	source = 1; break;

		case QE_BRG10:	source = 2; break;

		case QE_BRG15:	source = 3; break;

		case QE_BRG16:	source = 4; break;

		case QE_CLK3:	source = 5; break;

		case QE_CLK4:	source = 6; break;

		case QE_CLK17:	source = 7; break;

		case QE_CLK18:	source = 8; break;

		case QE_CLK7:	source = 9; break;

		case QE_CLK8:	source = 10; break;

		case QE_CLK16:	source = 11; break;

		default:	source = -1; break;

		case QE_BRG9:	clock_bits = 1; break;

		case QE_BRG10:	clock_bits = 2; break;

		case QE_BRG15:	clock_bits = 3; break;

		case QE_BRG16:	clock_bits = 4; break;

		case QE_CLK3:	clock_bits = 5; break;

		case QE_CLK4:	clock_bits = 6; break;

		case QE_CLK17:	clock_bits = 7; break;

		case QE_CLK18:	clock_bits = 8; break;

		case QE_CLK7:	clock_bits = 9; break;

		case QE_CLK8:	clock_bits = 10; break;

		case QE_CLK16:	clock_bits = 11; break;

		default: break;

		}

		break;

	case 4:

		switch (clock) {

		case QE_BRG13:	source = 1; break;

		case QE_BRG14:	source = 2; break;

		case QE_BRG15:	source = 3; break;

		case QE_BRG16:	source = 4; break;

		case QE_CLK5:	source = 5; break;

		case QE_CLK6:	source = 6; break;

		case QE_CLK21:	source = 7; break;

		case QE_CLK22:	source = 8; break;

		case QE_CLK7:	source = 9; break;

		case QE_CLK8:	source = 10; break;

		case QE_CLK16:	source = 11; break;

		default: 	source = -1; break;

		case QE_BRG13:	clock_bits = 1; break;

		case QE_BRG14:	clock_bits = 2; break;

		case QE_BRG15:	clock_bits = 3; break;

		case QE_BRG16:	clock_bits = 4; break;

		case QE_CLK5:	clock_bits = 5; break;

		case QE_CLK6:	clock_bits = 6; break;

		case QE_CLK21:	clock_bits = 7; break;

		case QE_CLK22:	clock_bits = 8; break;

		case QE_CLK7:	clock_bits = 9; break;

		case QE_CLK8:	clock_bits = 10; break;

		case QE_CLK16:	clock_bits = 11; break;

		default: break;

		}

		break;

	default:

		source = -1;

		break;

	default: break;

	}



	if (source == -1) {

		printk(KERN_ERR

		     "ucc_set_qe_mux_rxtx: Bad combination of clock and UCC.");

	/* Check for invalid combination of clock and UCC number */

	if (!clock_bits)

		return -ENOENT;

	}



	clock_bits = (u32) source;

	clock_mask = QE_CMXUCR_TX_CLK_SRC_MASK;

	if (mode == COMM_DIR_RX) {

		clock_bits <<= 4;  /* Rx field is 4 bits to left of Tx field */

		clock_mask <<= 4;  /* Rx field is 4 bits to left of Tx field */

	}

	clock_bits <<= shift;

	clock_mask <<= shift;

	if (mode == COMM_DIR_RX)

		shift += 4;



	out_be32(p_cmxucr, (in_be32(p_cmxucr) & ~clock_mask) | clock_bits);

	clrsetbits_be32(cmxucr, QE_CMXUCR_TX_CLK_SRC_MASK << shift,

		clock_bits << shift);



	return 0;

}

arch/powerpc/sysdev/qe_lib/ucc_fast.c

+61 −66
Original line number Diff line number Diff line
@@ -30,46 +30,45 @@ 


void ucc_fast_dump_regs(struct ucc_fast_private * uccf)

{

	printk(KERN_INFO "UCC%d Fast registers:", uccf->uf_info->ucc_num);

	printk(KERN_INFO "Base address: 0x%08x", (u32) uccf->uf_regs);



	printk(KERN_INFO "gumr  : addr - 0x%08x, val - 0x%08x",

		  (u32) & uccf->uf_regs->gumr, in_be32(&uccf->uf_regs->gumr));

	printk(KERN_INFO "upsmr : addr - 0x%08x, val - 0x%08x",

		  (u32) & uccf->uf_regs->upsmr, in_be32(&uccf->uf_regs->upsmr));

	printk(KERN_INFO "utodr : addr - 0x%08x, val - 0x%04x",

		  (u32) & uccf->uf_regs->utodr, in_be16(&uccf->uf_regs->utodr));

	printk(KERN_INFO "udsr  : addr - 0x%08x, val - 0x%04x",

		  (u32) & uccf->uf_regs->udsr, in_be16(&uccf->uf_regs->udsr));

	printk(KERN_INFO "ucce  : addr - 0x%08x, val - 0x%08x",

		  (u32) & uccf->uf_regs->ucce, in_be32(&uccf->uf_regs->ucce));

	printk(KERN_INFO "uccm  : addr - 0x%08x, val - 0x%08x",

		  (u32) & uccf->uf_regs->uccm, in_be32(&uccf->uf_regs->uccm));

	printk(KERN_INFO "uccs  : addr - 0x%08x, val - 0x%02x",

		  (u32) & uccf->uf_regs->uccs, uccf->uf_regs->uccs);

	printk(KERN_INFO "urfb  : addr - 0x%08x, val - 0x%08x",

		  (u32) & uccf->uf_regs->urfb, in_be32(&uccf->uf_regs->urfb));

	printk(KERN_INFO "urfs  : addr - 0x%08x, val - 0x%04x",

		  (u32) & uccf->uf_regs->urfs, in_be16(&uccf->uf_regs->urfs));

	printk(KERN_INFO "urfet : addr - 0x%08x, val - 0x%04x",

		  (u32) & uccf->uf_regs->urfet, in_be16(&uccf->uf_regs->urfet));

	printk(KERN_INFO "urfset: addr - 0x%08x, val - 0x%04x",

		  (u32) & uccf->uf_regs->urfset,

		  in_be16(&uccf->uf_regs->urfset));

	printk(KERN_INFO "utfb  : addr - 0x%08x, val - 0x%08x",

		  (u32) & uccf->uf_regs->utfb, in_be32(&uccf->uf_regs->utfb));

	printk(KERN_INFO "utfs  : addr - 0x%08x, val - 0x%04x",

		  (u32) & uccf->uf_regs->utfs, in_be16(&uccf->uf_regs->utfs));

	printk(KERN_INFO "utfet : addr - 0x%08x, val - 0x%04x",

		  (u32) & uccf->uf_regs->utfet, in_be16(&uccf->uf_regs->utfet));

	printk(KERN_INFO "utftt : addr - 0x%08x, val - 0x%04x",

		  (u32) & uccf->uf_regs->utftt, in_be16(&uccf->uf_regs->utftt));

	printk(KERN_INFO "utpt  : addr - 0x%08x, val - 0x%04x",

		  (u32) & uccf->uf_regs->utpt, in_be16(&uccf->uf_regs->utpt));

	printk(KERN_INFO "urtry : addr - 0x%08x, val - 0x%08x",

		  (u32) & uccf->uf_regs->urtry, in_be32(&uccf->uf_regs->urtry));

	printk(KERN_INFO "guemr : addr - 0x%08x, val - 0x%02x",

		  (u32) & uccf->uf_regs->guemr, uccf->uf_regs->guemr);

	printk(KERN_INFO "UCC%u Fast registers:\n", uccf->uf_info->ucc_num);

	printk(KERN_INFO "Base address: 0x%p\n", uccf->uf_regs);



	printk(KERN_INFO "gumr  : addr=0x%p, val=0x%08x\n",

		  &uccf->uf_regs->gumr, in_be32(&uccf->uf_regs->gumr));

	printk(KERN_INFO "upsmr : addr=0x%p, val=0x%08x\n",

		  &uccf->uf_regs->upsmr, in_be32(&uccf->uf_regs->upsmr));

	printk(KERN_INFO "utodr : addr=0x%p, val=0x%04x\n",

		  &uccf->uf_regs->utodr, in_be16(&uccf->uf_regs->utodr));

	printk(KERN_INFO "udsr  : addr=0x%p, val=0x%04x\n",

		  &uccf->uf_regs->udsr, in_be16(&uccf->uf_regs->udsr));

	printk(KERN_INFO "ucce  : addr=0x%p, val=0x%08x\n",

		  &uccf->uf_regs->ucce, in_be32(&uccf->uf_regs->ucce));

	printk(KERN_INFO "uccm  : addr=0x%p, val=0x%08x\n",

		  &uccf->uf_regs->uccm, in_be32(&uccf->uf_regs->uccm));

	printk(KERN_INFO "uccs  : addr=0x%p, val=0x%02x\n",

		  &uccf->uf_regs->uccs, uccf->uf_regs->uccs);

	printk(KERN_INFO "urfb  : addr=0x%p, val=0x%08x\n",

		  &uccf->uf_regs->urfb, in_be32(&uccf->uf_regs->urfb));

	printk(KERN_INFO "urfs  : addr=0x%p, val=0x%04x\n",

		  &uccf->uf_regs->urfs, in_be16(&uccf->uf_regs->urfs));

	printk(KERN_INFO "urfet : addr=0x%p, val=0x%04x\n",

		  &uccf->uf_regs->urfet, in_be16(&uccf->uf_regs->urfet));

	printk(KERN_INFO "urfset: addr=0x%p, val=0x%04x\n",

		  &uccf->uf_regs->urfset, in_be16(&uccf->uf_regs->urfset));

	printk(KERN_INFO "utfb  : addr=0x%p, val=0x%08x\n",

		  &uccf->uf_regs->utfb, in_be32(&uccf->uf_regs->utfb));

	printk(KERN_INFO "utfs  : addr=0x%p, val=0x%04x\n",

		  &uccf->uf_regs->utfs, in_be16(&uccf->uf_regs->utfs));

	printk(KERN_INFO "utfet : addr=0x%p, val=0x%04x\n",

		  &uccf->uf_regs->utfet, in_be16(&uccf->uf_regs->utfet));

	printk(KERN_INFO "utftt : addr=0x%p, val=0x%04x\n",

		  &uccf->uf_regs->utftt, in_be16(&uccf->uf_regs->utftt));

	printk(KERN_INFO "utpt  : addr=0x%p, val=0x%04x\n",

		  &uccf->uf_regs->utpt, in_be16(&uccf->uf_regs->utpt));

	printk(KERN_INFO "urtry : addr=0x%p, val=0x%08x\n",

		  &uccf->uf_regs->urtry, in_be32(&uccf->uf_regs->urtry));

	printk(KERN_INFO "guemr : addr=0x%p, val=0x%02x\n",

		  &uccf->uf_regs->guemr, uccf->uf_regs->guemr);

}

EXPORT_SYMBOL(ucc_fast_dump_regs);
@@ -149,55 +148,57 @@ int ucc_fast_init(struct ucc_fast_info * uf_info, struct ucc_fast_private ** ucc 


	/* check if the UCC port number is in range. */

	if ((uf_info->ucc_num < 0) || (uf_info->ucc_num > UCC_MAX_NUM - 1)) {

		printk(KERN_ERR "%s: illegal UCC number", __FUNCTION__);

		printk(KERN_ERR "%s: illegal UCC number\n", __FUNCTION__);

		return -EINVAL;

	}



	/* Check that 'max_rx_buf_length' is properly aligned (4). */

	if (uf_info->max_rx_buf_length & (UCC_FAST_MRBLR_ALIGNMENT - 1)) {

		printk(KERN_ERR "%s: max_rx_buf_length not aligned", __FUNCTION__);

		printk(KERN_ERR "%s: max_rx_buf_length not aligned\n",

			__FUNCTION__);

		return -EINVAL;

	}



	/* Validate Virtual Fifo register values */

	if (uf_info->urfs < UCC_FAST_URFS_MIN_VAL) {

		printk(KERN_ERR "%s: urfs is too small", __FUNCTION__);

		printk(KERN_ERR "%s: urfs is too small\n", __FUNCTION__);

		return -EINVAL;

	}



	if (uf_info->urfs & (UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT - 1)) {

		printk(KERN_ERR "%s: urfs is not aligned", __FUNCTION__);

		printk(KERN_ERR "%s: urfs is not aligned\n", __FUNCTION__);

		return -EINVAL;

	}



	if (uf_info->urfet & (UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT - 1)) {

		printk(KERN_ERR "%s: urfet is not aligned.", __FUNCTION__);

		printk(KERN_ERR "%s: urfet is not aligned.\n", __FUNCTION__);

		return -EINVAL;

	}



	if (uf_info->urfset & (UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT - 1)) {

		printk(KERN_ERR "%s: urfset is not aligned", __FUNCTION__);

		printk(KERN_ERR "%s: urfset is not aligned\n", __FUNCTION__);

		return -EINVAL;

	}



	if (uf_info->utfs & (UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT - 1)) {

		printk(KERN_ERR "%s: utfs is not aligned", __FUNCTION__);

		printk(KERN_ERR "%s: utfs is not aligned\n", __FUNCTION__);

		return -EINVAL;

	}



	if (uf_info->utfet & (UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT - 1)) {

		printk(KERN_ERR "%s: utfet is not aligned", __FUNCTION__);

		printk(KERN_ERR "%s: utfet is not aligned\n", __FUNCTION__);

		return -EINVAL;

	}



	if (uf_info->utftt & (UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT - 1)) {

		printk(KERN_ERR "%s: utftt is not aligned", __FUNCTION__);

		printk(KERN_ERR "%s: utftt is not aligned\n", __FUNCTION__);

		return -EINVAL;

	}



	uccf = kzalloc(sizeof(struct ucc_fast_private), GFP_KERNEL);

	if (!uccf) {

		printk(KERN_ERR "%s: Cannot allocate private data", __FUNCTION__);

		printk(KERN_ERR "%s: Cannot allocate private data\n",

			__FUNCTION__);

		return -ENOMEM;

	}
@@ -206,7 +207,7 @@ int ucc_fast_init(struct ucc_fast_info * uf_info, struct ucc_fast_private ** ucc 
	/* Set the PHY base address */

	uccf->uf_regs = ioremap(uf_info->regs, sizeof(struct ucc_fast));

	if (uccf->uf_regs == NULL) {

		printk(KERN_ERR "%s: Cannot map UCC registers", __FUNCTION__);

		printk(KERN_ERR "%s: Cannot map UCC registers\n", __FUNCTION__);

		return -ENOMEM;

	}
@@ -226,18 +227,10 @@ int ucc_fast_init(struct ucc_fast_info * uf_info, struct ucc_fast_private ** ucc 
	uccf->rx_discarded = 0;

#endif				/* STATISTICS */



	/* Init Guemr register */

	if ((ret = ucc_init_guemr((struct ucc_common *) (uf_regs)))) {

		printk(KERN_ERR "%s: cannot init GUEMR", __FUNCTION__);

		ucc_fast_free(uccf);

		return ret;

	}



	/* Set UCC to fast type */

	if ((ret = ucc_set_type(uf_info->ucc_num,

				(struct ucc_common *) (uf_regs),

				UCC_SPEED_TYPE_FAST))) {

		printk(KERN_ERR "%s: cannot set UCC type", __FUNCTION__);

	ret = ucc_set_type(uf_info->ucc_num, UCC_SPEED_TYPE_FAST);

	if (ret) {

		printk(KERN_ERR "%s: cannot set UCC type\n", __FUNCTION__);

		ucc_fast_free(uccf);

		return ret;

	}
@@ -276,7 +269,8 @@ int ucc_fast_init(struct ucc_fast_info * uf_info, struct ucc_fast_private ** ucc 
	uccf->ucc_fast_tx_virtual_fifo_base_offset =

	    qe_muram_alloc(uf_info->utfs, UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT);

	if (IS_ERR_VALUE(uccf->ucc_fast_tx_virtual_fifo_base_offset)) {

		printk(KERN_ERR "%s: cannot allocate MURAM for TX FIFO", __FUNCTION__);

		printk(KERN_ERR "%s: cannot allocate MURAM for TX FIFO\n",

			__FUNCTION__);

		uccf->ucc_fast_tx_virtual_fifo_base_offset = 0;

		ucc_fast_free(uccf);

		return -ENOMEM;
@@ -288,7 +282,8 @@ int ucc_fast_init(struct ucc_fast_info * uf_info, struct ucc_fast_private ** ucc 
			   UCC_FAST_RECEIVE_VIRTUAL_FIFO_SIZE_FUDGE_FACTOR,

			   UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT);

	if (IS_ERR_VALUE(uccf->ucc_fast_rx_virtual_fifo_base_offset)) {

		printk(KERN_ERR "%s: cannot allocate MURAM for RX FIFO", __FUNCTION__);

		printk(KERN_ERR "%s: cannot allocate MURAM for RX FIFO\n",

			__FUNCTION__);

		uccf->ucc_fast_rx_virtual_fifo_base_offset = 0;

		ucc_fast_free(uccf);

		return -ENOMEM;
@@ -318,7 +313,7 @@ int ucc_fast_init(struct ucc_fast_info * uf_info, struct ucc_fast_private ** ucc 
		if ((uf_info->rx_clock != QE_CLK_NONE) &&

		    ucc_set_qe_mux_rxtx(uf_info->ucc_num, uf_info->rx_clock,

					COMM_DIR_RX)) {

			printk(KERN_ERR "%s: illegal value for RX clock",

			printk(KERN_ERR "%s: illegal value for RX clock\n",

			       __FUNCTION__);

			ucc_fast_free(uccf);

			return -EINVAL;
@@ -327,7 +322,7 @@ int ucc_fast_init(struct ucc_fast_info * uf_info, struct ucc_fast_private ** ucc 
		if ((uf_info->tx_clock != QE_CLK_NONE) &&

		    ucc_set_qe_mux_rxtx(uf_info->ucc_num, uf_info->tx_clock,

					COMM_DIR_TX)) {

			printk(KERN_ERR "%s: illegal value for TX clock",

			printk(KERN_ERR "%s: illegal value for TX clock\n",

			       __FUNCTION__);

			ucc_fast_free(uccf);

			return -EINVAL;

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