Merge tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

		   - "samsung,exynos5260-pmu" - for Exynos5260 SoC.

		   - "samsung,exynos5260-pmu" - for Exynos5260 SoC.

		   - "samsung,exynos5410-pmu" - for Exynos5410 SoC,

		   - "samsung,exynos5410-pmu" - for Exynos5410 SoC,

		   - "samsung,exynos5420-pmu" - for Exynos5420 SoC.

		   - "samsung,exynos5420-pmu" - for Exynos5420 SoC.

		   - "samsung,exynos5433-pmu" - for Exynos5433 SoC.

		   - "samsung,exynos7-pmu" - for Exynos7 SoC.

		   - "samsung,exynos7-pmu" - for Exynos7 SoC.

		second value must be always "syscon".

		second value must be always "syscon".

Qualcomm External Bus Interface 2 (EBI2)

The EBI2 contains two peripheral blocks: XMEM and LCDC. The XMEM handles any

external memory (such as NAND or other memory-mapped peripherals) whereas

LCDC handles LCD displays.

As it says it connects devices to an external bus interface, meaning address

lines (up to 9 address lines so can only address 1KiB external memory space),

data lines (16 bits), OE (output enable), ADV (address valid, used on some

NOR flash memories), WE (write enable). This on top of 6 different chip selects

(CS0 thru CS5) so that in theory 6 different devices can be connected.

Apparently this bus is clocked at 64MHz. It has dedicated pins on the package

and the bus can only come out on these pins, however if some of the pins are

unused they can be left unconnected or remuxed to be used as GPIO or in some

cases other orthogonal functions as well.

Also CS1 and CS2 has -A and -B signals. Why they have that is unclear to me.

The chip selects have the following memory range assignments. This region of

memory is referred to as "Chip Peripheral SS FPB0" and is 168MB big.

Chip Select                     Physical address base

CS0 GPIO134                     0x1a800000-0x1b000000 (8MB)

CS1 GPIO39 (A) / GPIO123 (B)    0x1b000000-0x1b800000 (8MB)

CS2 GPIO40 (A) / GPIO124 (B)    0x1b800000-0x1c000000 (8MB)

CS3 GPIO133                     0x1d000000-0x25000000 (128 MB)

CS4 GPIO132                     0x1c800000-0x1d000000 (8MB)

CS5 GPIO131                     0x1c000000-0x1c800000 (8MB)

The APQ8060 Qualcomm Application Processor User Guide, 80-N7150-14 Rev. A,

August 6, 2012 contains some incomplete documentation of the EBI2.

FIXME: the manual mentions "write precharge cycles" and "precharge cycles".

We have not been able to figure out which bit fields these correspond to

in the hardware, or what valid values exist. The current hypothesis is that

this is something just used on the FAST chip selects and that the SLOW

chip selects are understood fully. There is also a "byte device enable"

flag somewhere for 8bit memories.

FIXME: The chipselects have SLOW and FAST configuration registers. It's a bit

unclear what this means, if they are mutually exclusive or can be used

together, or if some chip selects are hardwired to be FAST and others are SLOW

by design.

The XMEM registers are totally undocumented but could be partially decoded

because the Cypress AN49576 Antioch Westbridge apparently has suspiciously

similar register layout, see: http://www.cypress.com/file/105771/download

Required properties:

- compatible: should be one of:

  "qcom,msm8660-ebi2"

  "qcom,apq8060-ebi2"

- #address-cells: shoule be <2>: the first cell is the chipselect,

  the second cell is the offset inside the memory range

- #size-cells: should be <1>

- ranges: should be set to:

  ranges = <0 0x0 0x1a800000 0x00800000>,

           <1 0x0 0x1b000000 0x00800000>,

           <2 0x0 0x1b800000 0x00800000>,

           <3 0x0 0x1d000000 0x08000000>,

           <4 0x0 0x1c800000 0x00800000>,

           <5 0x0 0x1c000000 0x00800000>;

- reg: two ranges of registers: EBI2 config and XMEM config areas

- reg-names: should be "ebi2", "xmem"

- clocks: two clocks, EBI_2X and EBI

- clock-names: shoule be "ebi2x", "ebi2"

Optional subnodes:

- Nodes inside the EBI2 will be considered device nodes.

The following optional properties are properties that can be tagged onto

any device subnode. We are assuming that there can be only ONE device per

chipselect subnode, else the properties will become ambigous.

Optional properties arrays for SLOW chip selects:

- qcom,xmem-recovery-cycles: recovery cycles is the time the memory continues to

  drive the data bus after OE is de-asserted, in order to avoid contention on

  the data bus. They are inserted when reading one CS and switching to another

  CS or read followed by write on the same CS. Valid values 0 thru 15. Minimum

  value is actually 1, so a value of 0 will still yield 1 recovery cycle.

- qcom,xmem-write-hold-cycles: write hold cycles, these are extra cycles

  inserted after every write minimum 1. The data out is driven from the time

  WE is asserted until CS is asserted. With a hold of 1 (value = 0), the CS

  stays active for 1 extra cycle etc. Valid values 0 thru 15.

- qcom,xmem-write-delta-cycles: initial latency for write cycles inserted for

  the first write to a page or burst memory. Valid values 0 thru 255.

- qcom,xmem-read-delta-cycles: initial latency for read cycles inserted for the

  first read to a page or burst memory. Valid values 0 thru 255.

- qcom,xmem-write-wait-cycles: number of wait cycles for every write access, 0=1

  cycle. Valid values 0 thru 15.

- qcom,xmem-read-wait-cycles: number of wait cycles for every read access, 0=1

  cycle. Valid values 0 thru 15.

Optional properties arrays for FAST chip selects:

- qcom,xmem-address-hold-enable: this is a boolean property stating that we

  shall hold the address for an extra cycle to meet hold time requirements

  with ADV assertion.

- qcom,xmem-adv-to-oe-recovery-cycles: the number of cycles elapsed before an OE

  assertion, with respect to the cycle where ADV (address valid) is asserted.

  2 means 2 cycles between ADV and OE. Valid values 0, 1, 2 or 3.

- qcom,xmem-read-hold-cycles: the length in cycles of the first segment of a

  read transfer. For a single read trandfer this will be the time from CS

  assertion to OE assertion. Valid values 0 thru 15.

Example:

ebi2@1a100000 {

	compatible = "qcom,apq8060-ebi2";

	#address-cells = <2>;

	#size-cells = <1>;

	ranges = <0 0x0 0x1a800000 0x00800000>,

		 <1 0x0 0x1b000000 0x00800000>,

		 <2 0x0 0x1b800000 0x00800000>,

		 <3 0x0 0x1d000000 0x08000000>,

		 <4 0x0 0x1c800000 0x00800000>,

		 <5 0x0 0x1c000000 0x00800000>;

	reg = <0x1a100000 0x1000>, <0x1a110000 0x1000>;

	reg-names = "ebi2", "xmem";

	clocks = <&gcc EBI2_2X_CLK>, <&gcc EBI2_CLK>;

	clock-names = "ebi2x", "ebi2";

	/* Make sure to set up the pin control for the EBI2 */

	pinctrl-names = "default";

	pinctrl-0 = <&foo_ebi2_pins>;

	foo-ebi2@2,0 {

		compatible = "foo";

		reg = <2 0x0 0x100>;

		(...)

		qcom,xmem-recovery-cycles = <0>;

		qcom,xmem-write-hold-cycles = <3>;

		qcom,xmem-write-delta-cycles = <31>;

		qcom,xmem-read-delta-cycles = <28>;

		qcom,xmem-write-wait-cycles = <9>;

		qcom,xmem-read-wait-cycles = <9>;

	};

};

	"marvell,dove-core-clock" - for Dove SoC core clocks

	"marvell,dove-core-clock" - for Dove SoC core clocks

	"marvell,kirkwood-core-clock" - for Kirkwood SoC (except mv88f6180)

	"marvell,kirkwood-core-clock" - for Kirkwood SoC (except mv88f6180)

	"marvell,mv88f6180-core-clock" - for Kirkwood MV88f6180 SoC

	"marvell,mv88f6180-core-clock" - for Kirkwood MV88f6180 SoC

	"marvell,mv88f5181-core-clock" - for Orion MV88F5181 SoC

	"marvell,mv88f5182-core-clock" - for Orion MV88F5182 SoC

	"marvell,mv88f5182-core-clock" - for Orion MV88F5182 SoC

	"marvell,mv88f5281-core-clock" - for Orion MV88F5281 SoC

	"marvell,mv88f5281-core-clock" - for Orion MV88F5281 SoC

	"marvell,mv88f6183-core-clock" - for Orion MV88F6183 SoC

	"marvell,mv88f6183-core-clock" - for Orion MV88F6183 SoC

STMicroelectronics STM32 Reset and Clock Controller

STMicroelectronics STM32 Reset and Clock Controller

===================================================

===================================================

The RCC IP is both a reset and a clock controller. This documentation only

The RCC IP is both a reset and a clock controller.

describes the clock part.

Please also refer to clock-bindings.txt in this directory for common clock

Please refer to clock-bindings.txt for common clock controller binding usage.

controller binding usage.

Please also refer to reset.txt for common reset controller binding usage.

Required properties:

Required properties:

- compatible: Should be "st,stm32f42xx-rcc"

- compatible: Should be "st,stm32f42xx-rcc"

- reg: should be register base and length as documented in the

- reg: should be register base and length as documented in the

  datasheet

  datasheet

- #reset-cells: 1, see below

- #clock-cells: 2, device nodes should specify the clock in their "clocks"

- #clock-cells: 2, device nodes should specify the clock in their "clocks"

  property, containing a phandle to the clock device node, an index selecting

  property, containing a phandle to the clock device node, an index selecting

  between gated clocks and other clocks and an index specifying the clock to

  between gated clocks and other clocks and an index specifying the clock to

Example:

Example:

	rcc: rcc@40023800 {

	rcc: rcc@40023800 {

		#reset-cells = <1>;

		#clock-cells = <2>

		#clock-cells = <2>

		compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";

		compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";

		reg = <0x40023800 0x400>;

		reg = <0x40023800 0x400>;

It is calculated as: index = register_offset / 4 * 32 + bit_offset.

It is calculated as: index = register_offset / 4 * 32 + bit_offset.

Where bit_offset is the bit offset within the register (LSB is 0, MSB is 31).

Where bit_offset is the bit offset within the register (LSB is 0, MSB is 31).

To simplify the usage and to share bit definition with the reset and clock

drivers of the RCC IP, macros are available to generate the index in

human-readble format.

For STM32F4 series, the macro are available here:

 - include/dt-bindings/mfd/stm32f4-rcc.h

Example:

Example:

	/* Gated clock, AHB1 bit 0 (GPIOA) */

	/* Gated clock, AHB1 bit 0 (GPIOA) */

	... {

	... {

		clocks = <&rcc 0 0>

		clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOA)>

	};

	};

	/* Gated clock, AHB2 bit 4 (CRYP) */

	/* Gated clock, AHB2 bit 4 (CRYP) */

	... {

	... {

		clocks = <&rcc 0 36>

		clocks = <&rcc 0 STM32F4_AHB2_CLOCK(CRYP)>

	};

	};

Specifying other clocks

Specifying other clocks

	/* Misc clock, FCLK */

	/* Misc clock, FCLK */

	... {

	... {

		clocks = <&rcc 1 1>

		clocks = <&rcc 1 STM32F4_APB1_CLOCK(TIM2)>

	};

Specifying softreset control of devices

=======================================

Device nodes should specify the reset channel required in their "resets"

property, containing a phandle to the reset device node and an index specifying

which channel to use.

The index is the bit number within the RCC registers bank, starting from RCC

base address.

It is calculated as: index = register_offset / 4 * 32 + bit_offset.

Where bit_offset is the bit offset within the register.

For example, for CRC reset:

  crc = AHB1RSTR_offset / 4 * 32 + CRCRST_bit_offset = 0x10 / 4 * 32 + 12 = 140

example:

	timer2 {

		resets	= <&rcc STM32F4_APB1_RESET(TIM2)>;

	};

	};

* APM X-Gene SoC PMU bindings

This is APM X-Gene SoC PMU (Performance Monitoring Unit) module.

The following PMU devices are supported:

  L3C			- L3 cache controller

  IOB			- IO bridge

  MCB			- Memory controller bridge

  MC			- Memory controller

The following section describes the SoC PMU DT node binding.

Required properties:

- compatible		: Shall be "apm,xgene-pmu" for revision 1 or

                          "apm,xgene-pmu-v2" for revision 2.

- regmap-csw		: Regmap of the CPU switch fabric (CSW) resource.

- regmap-mcba		: Regmap of the MCB-A (memory bridge) resource.

- regmap-mcbb		: Regmap of the MCB-B (memory bridge) resource.

- reg			: First resource shall be the CPU bus PMU resource.

- interrupts            : Interrupt-specifier for PMU IRQ.

Required properties for L3C subnode:

- compatible		: Shall be "apm,xgene-pmu-l3c".

- reg			: First resource shall be the L3C PMU resource.

Required properties for IOB subnode:

- compatible		: Shall be "apm,xgene-pmu-iob".

- reg			: First resource shall be the IOB PMU resource.

Required properties for MCB subnode:

- compatible		: Shall be "apm,xgene-pmu-mcb".

- reg			: First resource shall be the MCB PMU resource.

- enable-bit-index	: The bit indicates if the according MCB is enabled.

Required properties for MC subnode:

- compatible		: Shall be "apm,xgene-pmu-mc".

- reg			: First resource shall be the MC PMU resource.

- enable-bit-index	: The bit indicates if the according MC is enabled.

Example:

	csw: csw@7e200000 {

		compatible = "apm,xgene-csw", "syscon";

		reg = <0x0 0x7e200000 0x0 0x1000>;

	};

	mcba: mcba@7e700000 {

		compatible = "apm,xgene-mcb", "syscon";

		reg = <0x0 0x7e700000 0x0 0x1000>;

	};

	mcbb: mcbb@7e720000 {

		compatible = "apm,xgene-mcb", "syscon";

		reg = <0x0 0x7e720000 0x0 0x1000>;

	};

	pmu: pmu@78810000 {

		compatible = "apm,xgene-pmu-v2";

		#address-cells = <2>;

		#size-cells = <2>;

		ranges;

		regmap-csw = <&csw>;

		regmap-mcba = <&mcba>;

		regmap-mcbb = <&mcbb>;

		reg = <0x0 0x78810000 0x0 0x1000>;

		interrupts = <0x0 0x22 0x4>;

		pmul3c@7e610000 {

			compatible = "apm,xgene-pmu-l3c";

			reg = <0x0 0x7e610000 0x0 0x1000>;

		};

		pmuiob@7e940000 {

			compatible = "apm,xgene-pmu-iob";

			reg = <0x0 0x7e940000 0x0 0x1000>;

		};

		pmucmcb@7e710000 {

			compatible = "apm,xgene-pmu-mcb";

			reg = <0x0 0x7e710000 0x0 0x1000>;

			enable-bit-index = <0>;

		};

		pmucmcb@7e730000 {

			compatible = "apm,xgene-pmu-mcb";

			reg = <0x0 0x7e730000 0x0 0x1000>;

			enable-bit-index = <1>;

		};

		pmucmc@7e810000 {

			compatible = "apm,xgene-pmu-mc";

			reg = <0x0 0x7e810000 0x0 0x1000>;

			enable-bit-index = <0>;

		};

		pmucmc@7e850000 {

			compatible = "apm,xgene-pmu-mc";

			reg = <0x0 0x7e850000 0x0 0x1000>;

			enable-bit-index = <1>;

		};

		pmucmc@7e890000 {

			compatible = "apm,xgene-pmu-mc";

			reg = <0x0 0x7e890000 0x0 0x1000>;

			enable-bit-index = <2>;

		};

		pmucmc@7e8d0000 {

			compatible = "apm,xgene-pmu-mc";

			reg = <0x0 0x7e8d0000 0x0 0x1000>;

			enable-bit-index = <3>;

		};

	};