Commit 6aebde8d authored by Michal Kalderon's avatar Michal Kalderon Committed by David S. Miller
Browse files

qed: FW 8.42.2.0 Expose new registers and change windows 



This patch contains register initialization related changes.
- Modifications to the runtime offsets - these are defines used
  by the driver or firmware functions to set values that are used
  by the initialization functions to set device register values.
- Global window values changes to provide different device register
  ranges.
- Additional device registers addresses were added to the register file,
  used in later stages.

Signed-off-by: default avatarAriel Elior <ariel.elior@marvell.com>
Signed-off-by: default avatarMichal Kalderon <michal.kalderon@marvell.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 2924e069

drivers/net/ethernet/qlogic/qed/qed_hsi.h

+438 −523

File changed.

Preview size limit exceeded, changes collapsed.

drivers/net/ethernet/qlogic/qed/qed_init_fw_funcs.c

+3 −6
Original line number Diff line number Diff line
@@ -44,9 +44,9 @@ 
#define CDU_VALIDATION_DEFAULT_CFG	61



static u16 con_region_offsets[3][NUM_OF_CONNECTION_TYPES_E4] = {

	{400, 336, 352, 304, 304, 384, 416, 352},	/* region 3 offsets */

	{528, 496, 416, 448, 448, 512, 544, 480},	/* region 4 offsets */

	{608, 544, 496, 512, 576, 592, 624, 560}	/* region 5 offsets */

	{400, 336, 352, 368, 304, 384, 416, 352},	/* region 3 offsets */

	{528, 496, 416, 512, 448, 512, 544, 480},	/* region 4 offsets */

	{608, 544, 496, 576, 576, 592, 624, 560}	/* region 5 offsets */

};



static u16 task_region_offsets[1][NUM_OF_CONNECTION_TYPES_E4] = {
@@ -228,9 +228,6 @@ static void qed_enable_pf_rl(struct qed_hwfn *p_hwfn, bool pf_rl_en) 
		STORE_RT_REG(p_hwfn,

			     QM_REG_RLPFVOQENABLE_RT_OFFSET,

			     (u32)voq_bit_mask);

		if (num_ext_voqs >= 32)

			STORE_RT_REG(p_hwfn, QM_REG_RLPFVOQENABLE_MSB_RT_OFFSET,

				     (u32)(voq_bit_mask >> 32));



		/* Write RL period */

		STORE_RT_REG(p_hwfn,

drivers/net/ethernet/qlogic/qed/qed_init_ops.c

+9 −9
Original line number Diff line number Diff line
@@ -54,15 +54,15 @@ static u32 pxp_global_win[] = { 
	0x1c80, /* win 3: addr=0x1c80000, size=4096 bytes */

	0x1d00, /* win 4: addr=0x1d00000, size=4096 bytes */

	0x1d01, /* win 5: addr=0x1d01000, size=4096 bytes */

	0x1d80, /* win 6: addr=0x1d80000, size=4096 bytes */

	0x1d81, /* win 7: addr=0x1d81000, size=4096 bytes */

	0x1d82, /* win 8: addr=0x1d82000, size=4096 bytes */

	0x1e00, /* win 9: addr=0x1e00000, size=4096 bytes */

	0x1e80, /* win 10: addr=0x1e80000, size=4096 bytes */

	0x1f00, /* win 11: addr=0x1f00000, size=4096 bytes */

	0,

	0,

	0,

	0x1d02, /* win 6: addr=0x1d02000, size=4096 bytes */

	0x1d80, /* win 7: addr=0x1d80000, size=4096 bytes */

	0x1d81, /* win 8: addr=0x1d81000, size=4096 bytes */

	0x1d82, /* win 9: addr=0x1d82000, size=4096 bytes */

	0x1e00, /* win 10: addr=0x1e00000, size=4096 bytes */

	0x1e01, /* win 11: addr=0x1e01000, size=4096 bytes */

	0x1e80, /* win 12: addr=0x1e80000, size=4096 bytes */

	0x1f00, /* win 13: addr=0x1f00000, size=4096 bytes */

	0x1c08, /* win 14: addr=0x1c08000, size=4096 bytes */

	0,

	0,

	0,

drivers/net/ethernet/qlogic/qed/qed_reg_addr.h

+38 −0
Original line number Diff line number Diff line
@@ -178,6 +178,8 @@ 
	0x008c80UL

#define  MCP_REG_SCRATCH	\

	0xe20000UL

#define MCP_REG_SCRATCH_SIZE \

	57344

#define  CNIG_REG_NW_PORT_MODE_BB \

	0x218200UL

#define  MISCS_REG_CHIP_NUM \
@@ -212,6 +214,8 @@ 
	0x580900UL

#define  DBG_REG_CLIENT_ENABLE \

	0x010004UL

#define DBG_REG_TIMESTAMP_VALID_EN \

	0x010b58UL

#define  DMAE_REG_INIT \

	0x00c000UL

#define  DORQ_REG_IFEN \
@@ -350,6 +354,10 @@ 
	0x24000cUL

#define PSWRQ2_REG_ILT_MEMORY \

	0x260000UL

#define PSWRQ2_REG_ILT_MEMORY_SIZE_BB \

	15200

#define PSWRQ2_REG_ILT_MEMORY_SIZE_K2 \

	22000

#define  PSWHST_REG_DISCARD_INTERNAL_WRITES \

	0x2a0040UL

#define  PSWHST2_REG_DBGSYN_ALMOST_FULL_THR \
@@ -1453,6 +1461,8 @@ 
	0x1401404UL

#define XSEM_REG_DBG_FRAME_MODE_BB_K2	\

	0x1401408UL

#define XSEM_REG_DBG_GPRE_VECT \

	0x1401410UL

#define XSEM_REG_DBG_MODE1_CFG_BB_K2 \

	0x1401420UL

#define XSEM_REG_FAST_MEMORY \
@@ -1465,6 +1475,8 @@ 
	0x1501404UL

#define YSEM_REG_DBG_FRAME_MODE_BB_K2	\

	0x1501408UL

#define YSEM_REG_DBG_GPRE_VECT \

	0x1501410UL

#define YSEM_REG_DBG_MODE1_CFG_BB_K2 \

	0x1501420UL

#define YSEM_REG_FAST_MEMORY \
@@ -1479,6 +1491,8 @@ 
	0x1601404UL

#define PSEM_REG_DBG_FRAME_MODE_BB_K2	\

	0x1601408UL

#define PSEM_REG_DBG_GPRE_VECT \

	0x1601410UL

#define PSEM_REG_DBG_MODE1_CFG_BB_K2 \

	0x1601420UL

#define PSEM_REG_FAST_MEMORY \
@@ -1493,6 +1507,8 @@ 
	0x1701404UL

#define TSEM_REG_DBG_FRAME_MODE_BB_K2	\

	0x1701408UL

#define TSEM_REG_DBG_GPRE_VECT \

	0x1701410UL

#define TSEM_REG_DBG_MODE1_CFG_BB_K2 \

	0x1701420UL

#define TSEM_REG_FAST_MEMORY \
@@ -1507,12 +1523,16 @@ 
	0x1801404UL

#define MSEM_REG_DBG_FRAME_MODE_BB_K2	\

	0x1801408UL

#define MSEM_REG_DBG_GPRE_VECT \

	0x1801410UL

#define MSEM_REG_DBG_MODE1_CFG_BB_K2 \

	0x1801420UL

#define MSEM_REG_FAST_MEMORY \

	0x1840000UL

#define USEM_REG_SLOW_DBG_EMPTY_BB_K2	\

	0x1901140UL

#define SEM_FAST_REG_INT_RAM_SIZE \

	20480

#define USEM_REG_SYNC_DBG_EMPTY	\

	0x1901160UL

#define USEM_REG_SLOW_DBG_ACTIVE_BB_K2 \
@@ -1521,14 +1541,26 @@ 
	0x1901404UL

#define USEM_REG_DBG_FRAME_MODE_BB_K2	\

	0x1901408UL

#define USEM_REG_DBG_GPRE_VECT \

	0x1901410UL

#define USEM_REG_DBG_MODE1_CFG_BB_K2 \

	0x1901420UL

#define USEM_REG_FAST_MEMORY \

	0x1940000UL

#define SEM_FAST_REG_DBG_MODE23_SRC_DISABLE \

	0x000748UL

#define SEM_FAST_REG_DBG_MODE4_SRC_DISABLE \

	0x00074cUL

#define SEM_FAST_REG_DBG_MODE6_SRC_DISABLE \

	0x000750UL

#define SEM_FAST_REG_DEBUG_ACTIVE \

	0x000740UL

#define SEM_FAST_REG_INT_RAM \

	0x020000UL

#define SEM_FAST_REG_INT_RAM_SIZE_BB_K2 \

	20480

#define SEM_FAST_REG_RECORD_FILTER_ENABLE \

	0x000768UL

#define GRC_REG_TRACE_FIFO_VALID_DATA \

	0x050064UL

#define GRC_REG_NUMBER_VALID_OVERRIDE_WINDOW \
@@ -1583,14 +1615,20 @@ 
	0x181530UL

#define DBG_REG_DBG_BLOCK_ON \

	0x010454UL

#define DBG_REG_FILTER_ENABLE \

	0x0109d0UL

#define DBG_REG_FRAMING_MODE \

	0x010058UL

#define DBG_REG_TRIGGER_ENABLE \

	0x01054cUL

#define SEM_FAST_REG_VFC_DATA_WR \

	0x000b40UL

#define SEM_FAST_REG_VFC_ADDR \

	0x000b44UL

#define SEM_FAST_REG_VFC_DATA_RD \

	0x000b48UL

#define SEM_FAST_REG_VFC_STATUS	\

	0x000b4cUL

#define RSS_REG_RSS_RAM_DATA \

	0x238c20UL

#define RSS_REG_RSS_RAM_DATA_SIZE \

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