ASoC: meson: aiu: add i2s and spdif support (6ae9ca9c) · Commits · 戴 / test

sound/soc/meson/Kconfig

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Original line number	Diff line number	Diff line
		@@ -2,6 +2,13 @@
		menu "ASoC support for Amlogic platforms"
		depends on ARCH_MESON \|\| COMPILE_TEST

		config SND_MESON_AIU
		tristate "Amlogic AIU"
		select SND_PCM_IEC958
		help
		Select Y or M to add support for the Audio output subsystem found
		in the Amlogic GX SoC family

		config SND_MESON_AXG_FIFO
		tristate
		select REGMAP_MMIO

sound/soc/meson/Makefile

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		# SPDX-License-Identifier: (GPL-2.0 OR MIT)

		snd-soc-meson-aiu-objs := aiu.o
		snd-soc-meson-aiu-objs += aiu-encoder-i2s.o
		snd-soc-meson-aiu-objs += aiu-encoder-spdif.o
		snd-soc-meson-aiu-objs += aiu-fifo.o
		snd-soc-meson-aiu-objs += aiu-fifo-i2s.o
		snd-soc-meson-aiu-objs += aiu-fifo-spdif.o
		snd-soc-meson-axg-fifo-objs := axg-fifo.o
		snd-soc-meson-axg-frddr-objs := axg-frddr.o
		snd-soc-meson-axg-toddr-objs := axg-toddr.o
		@@ -14,6 +20,7 @@ snd-soc-meson-axg-pdm-objs := axg-pdm.o
		snd-soc-meson-codec-glue-objs := meson-codec-glue.o
		snd-soc-meson-g12a-tohdmitx-objs := g12a-tohdmitx.o

		obj-$(CONFIG_SND_MESON_AIU) += snd-soc-meson-aiu.o
		obj-$(CONFIG_SND_MESON_AXG_FIFO) += snd-soc-meson-axg-fifo.o
		obj-$(CONFIG_SND_MESON_AXG_FRDDR) += snd-soc-meson-axg-frddr.o
		obj-$(CONFIG_SND_MESON_AXG_TODDR) += snd-soc-meson-axg-toddr.o

sound/soc/meson/aiu-encoder-i2s.c

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		// SPDX-License-Identifier: GPL-2.0
		//
		// Copyright (c) 2020 BayLibre, SAS.
		// Author: Jerome Brunet <jbrunet@baylibre.com>

		#include <linux/bitfield.h>
		#include <linux/clk.h>
		#include <sound/pcm_params.h>
		#include <sound/soc.h>
		#include <sound/soc-dai.h>

		#include "aiu.h"

		#define AIU_I2S_SOURCE_DESC_MODE_8CH BIT(0)
		#define AIU_I2S_SOURCE_DESC_MODE_24BIT BIT(5)
		#define AIU_I2S_SOURCE_DESC_MODE_32BIT BIT(9)
		#define AIU_I2S_SOURCE_DESC_MODE_SPLIT BIT(11)
		#define AIU_RST_SOFT_I2S_FAST BIT(0)

		#define AIU_I2S_DAC_CFG_MSB_FIRST BIT(2)
		#define AIU_I2S_MISC_HOLD_EN BIT(2)
		#define AIU_CLK_CTRL_I2S_DIV_EN BIT(0)
		#define AIU_CLK_CTRL_I2S_DIV GENMASK(3, 2)
		#define AIU_CLK_CTRL_AOCLK_INVERT BIT(6)
		#define AIU_CLK_CTRL_LRCLK_INVERT BIT(7)
		#define AIU_CLK_CTRL_LRCLK_SKEW GENMASK(9, 8)
		#define AIU_CLK_CTRL_MORE_HDMI_AMCLK BIT(6)
		#define AIU_CLK_CTRL_MORE_I2S_DIV GENMASK(5, 0)
		#define AIU_CODEC_DAC_LRCLK_CTRL_DIV GENMASK(11, 0)

		struct aiu_encoder_i2s {
		struct clk *aoclk;
		struct clk *mclk;
		struct clk *mixer;
		struct clk *pclk;
		};

		static void aiu_encoder_i2s_divider_enable(struct snd_soc_component *component,
		bool enable)
		{
		snd_soc_component_update_bits(component, AIU_CLK_CTRL,
		AIU_CLK_CTRL_I2S_DIV_EN,
		enable ? AIU_CLK_CTRL_I2S_DIV_EN : 0);
		}

		static void aiu_encoder_i2s_hold(struct snd_soc_component *component,
		bool enable)
		{
		snd_soc_component_update_bits(component, AIU_I2S_MISC,
		AIU_I2S_MISC_HOLD_EN,
		enable ? AIU_I2S_MISC_HOLD_EN : 0);
		}

		static int aiu_encoder_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
		struct snd_soc_dai *dai)
		{
		struct snd_soc_component *component = dai->component;

		switch (cmd) {
		case SNDRV_PCM_TRIGGER_START:
		case SNDRV_PCM_TRIGGER_RESUME:
		case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
		aiu_encoder_i2s_hold(component, false);
		return 0;

		case SNDRV_PCM_TRIGGER_STOP:
		case SNDRV_PCM_TRIGGER_SUSPEND:
		case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
		aiu_encoder_i2s_hold(component, true);
		return 0;

		default:
		return -EINVAL;
		}
		}

		static int aiu_encoder_i2s_setup_desc(struct snd_soc_component *component,
		struct snd_pcm_hw_params *params)
		{
		/* Always operate in split (classic interleaved) mode */
		unsigned int desc = AIU_I2S_SOURCE_DESC_MODE_SPLIT;
		unsigned int val;

		/* Reset required to update the pipeline */
		snd_soc_component_write(component, AIU_RST_SOFT, AIU_RST_SOFT_I2S_FAST);
		snd_soc_component_read(component, AIU_I2S_SYNC, &val);

		switch (params_physical_width(params)) {
		case 16: /* Nothing to do */
		break;

		case 32:
		desc \|= (AIU_I2S_SOURCE_DESC_MODE_24BIT \|
		AIU_I2S_SOURCE_DESC_MODE_32BIT);
		break;

		default:
		return -EINVAL;
		}

		switch (params_channels(params)) {
		case 2: /* Nothing to do */
		break;
		case 8:
		desc \|= AIU_I2S_SOURCE_DESC_MODE_8CH;
		break;
		default:
		return -EINVAL;
		}

		snd_soc_component_update_bits(component, AIU_I2S_SOURCE_DESC,
		AIU_I2S_SOURCE_DESC_MODE_8CH \|
		AIU_I2S_SOURCE_DESC_MODE_24BIT \|
		AIU_I2S_SOURCE_DESC_MODE_32BIT \|
		AIU_I2S_SOURCE_DESC_MODE_SPLIT,
		desc);

		return 0;
		}

		static int aiu_encoder_i2s_set_clocks(struct snd_soc_component *component,
		struct snd_pcm_hw_params *params)
		{
		struct aiu *aiu = snd_soc_component_get_drvdata(component);
		unsigned int srate = params_rate(params);
		unsigned int fs, bs;

		/* Get the oversampling factor */
		fs = DIV_ROUND_CLOSEST(clk_get_rate(aiu->i2s.clks[MCLK].clk), srate);

		if (fs % 64)
		return -EINVAL;

		/* Send data MSB first */
		snd_soc_component_update_bits(component, AIU_I2S_DAC_CFG,
		AIU_I2S_DAC_CFG_MSB_FIRST,
		AIU_I2S_DAC_CFG_MSB_FIRST);

		/* Set bclk to lrlck ratio */
		snd_soc_component_update_bits(component, AIU_CODEC_DAC_LRCLK_CTRL,
		AIU_CODEC_DAC_LRCLK_CTRL_DIV,
		FIELD_PREP(AIU_CODEC_DAC_LRCLK_CTRL_DIV,
		64 - 1));

		/* Use CLK_MORE for mclk to bclk divider */
		snd_soc_component_update_bits(component, AIU_CLK_CTRL,
		AIU_CLK_CTRL_I2S_DIV, 0);

		/*
		* NOTE: this HW is odd.
		* In most configuration, the i2s divider is 'mclk / blck'.
		* However, in 16 bits - 8ch mode, this factor needs to be
		* increased by 50% to get the correct output rate.
		* No idea why !
		*/
		bs = fs / 64;
		if (params_width(params) == 16 && params_channels(params) == 8) {
		if (bs % 2) {
		dev_err(component->dev,
		"Cannot increase i2s divider by 50%%\n");
		return -EINVAL;
		}
		bs += bs / 2;
		}

		snd_soc_component_update_bits(component, AIU_CLK_CTRL_MORE,
		AIU_CLK_CTRL_MORE_I2S_DIV,
		FIELD_PREP(AIU_CLK_CTRL_MORE_I2S_DIV,
		bs - 1));

		/* Make sure amclk is used for HDMI i2s as well */
		snd_soc_component_update_bits(component, AIU_CLK_CTRL_MORE,
		AIU_CLK_CTRL_MORE_HDMI_AMCLK,
		AIU_CLK_CTRL_MORE_HDMI_AMCLK);

		return 0;
		}

		static int aiu_encoder_i2s_hw_params(struct snd_pcm_substream *substream,
		struct snd_pcm_hw_params *params,
		struct snd_soc_dai *dai)
		{
		struct snd_soc_component *component = dai->component;
		int ret;

		/* Disable the clock while changing the settings */
		aiu_encoder_i2s_divider_enable(component, false);

		ret = aiu_encoder_i2s_setup_desc(component, params);
		if (ret) {
		dev_err(dai->dev, "setting i2s desc failed\n");
		return ret;
		}

		ret = aiu_encoder_i2s_set_clocks(component, params);
		if (ret) {
		dev_err(dai->dev, "setting i2s clocks failed\n");
		return ret;
		}

		aiu_encoder_i2s_divider_enable(component, true);

		return 0;
		}

		static int aiu_encoder_i2s_hw_free(struct snd_pcm_substream *substream,
		struct snd_soc_dai *dai)
		{
		struct snd_soc_component *component = dai->component;

		aiu_encoder_i2s_divider_enable(component, false);

		return 0;
		}

		static int aiu_encoder_i2s_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
		{
		struct snd_soc_component *component = dai->component;
		unsigned int inv = fmt & SND_SOC_DAIFMT_INV_MASK;
		unsigned int val = 0;
		unsigned int skew;

		/* Only CPU Master / Codec Slave supported ATM */
		if ((fmt & SND_SOC_DAIFMT_MASTER_MASK) != SND_SOC_DAIFMT_CBS_CFS)
		return -EINVAL;

		if (inv == SND_SOC_DAIFMT_NB_IF \|\|
		inv == SND_SOC_DAIFMT_IB_IF)
		val \|= AIU_CLK_CTRL_LRCLK_INVERT;

		if (inv == SND_SOC_DAIFMT_IB_NF \|\|
		inv == SND_SOC_DAIFMT_IB_IF)
		val \|= AIU_CLK_CTRL_AOCLK_INVERT;

		/* Signal skew */
		switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
		case SND_SOC_DAIFMT_I2S:
		/* Invert sample clock for i2s */
		val ^= AIU_CLK_CTRL_LRCLK_INVERT;
		skew = 1;
		break;
		case SND_SOC_DAIFMT_LEFT_J:
		skew = 0;
		break;
		default:
		return -EINVAL;
		}

		val \|= FIELD_PREP(AIU_CLK_CTRL_LRCLK_SKEW, skew);
		snd_soc_component_update_bits(component, AIU_CLK_CTRL,
		AIU_CLK_CTRL_LRCLK_INVERT \|
		AIU_CLK_CTRL_AOCLK_INVERT \|
		AIU_CLK_CTRL_LRCLK_SKEW,
		val);

		return 0;
		}

		static int aiu_encoder_i2s_set_sysclk(struct snd_soc_dai *dai, int clk_id,
		unsigned int freq, int dir)
		{
		struct aiu *aiu = snd_soc_component_get_drvdata(dai->component);
		int ret;

		if (WARN_ON(clk_id != 0))
		return -EINVAL;

		if (dir == SND_SOC_CLOCK_IN)
		return 0;

		ret = clk_set_rate(aiu->i2s.clks[MCLK].clk, freq);
		if (ret)
		dev_err(dai->dev, "Failed to set sysclk to %uHz", freq);

		return ret;
		}

		static const unsigned int hw_channels[] = {2, 8};
		static const struct snd_pcm_hw_constraint_list hw_channel_constraints = {
		.list = hw_channels,
		.count = ARRAY_SIZE(hw_channels),
		.mask = 0,
		};

		static int aiu_encoder_i2s_startup(struct snd_pcm_substream *substream,
		struct snd_soc_dai *dai)
		{
		struct aiu *aiu = snd_soc_component_get_drvdata(dai->component);
		int ret;

		/* Make sure the encoder gets either 2 or 8 channels */
		ret = snd_pcm_hw_constraint_list(substream->runtime, 0,
		SNDRV_PCM_HW_PARAM_CHANNELS,
		&hw_channel_constraints);
		if (ret) {
		dev_err(dai->dev, "adding channels constraints failed\n");
		return ret;
		}

		ret = clk_bulk_prepare_enable(aiu->i2s.clk_num, aiu->i2s.clks);
		if (ret)
		dev_err(dai->dev, "failed to enable i2s clocks\n");

		return ret;
		}

		static void aiu_encoder_i2s_shutdown(struct snd_pcm_substream *substream,
		struct snd_soc_dai *dai)
		{
		struct aiu *aiu = snd_soc_component_get_drvdata(dai->component);

		clk_bulk_disable_unprepare(aiu->i2s.clk_num, aiu->i2s.clks);
		}

		const struct snd_soc_dai_ops aiu_encoder_i2s_dai_ops = {
		.trigger = aiu_encoder_i2s_trigger,
		.hw_params = aiu_encoder_i2s_hw_params,
		.hw_free = aiu_encoder_i2s_hw_free,
		.set_fmt = aiu_encoder_i2s_set_fmt,
		.set_sysclk = aiu_encoder_i2s_set_sysclk,
		.startup = aiu_encoder_i2s_startup,
		.shutdown = aiu_encoder_i2s_shutdown,
		};

sound/soc/meson/aiu-encoder-spdif.c

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		// SPDX-License-Identifier: GPL-2.0
		//
		// Copyright (c) 2020 BayLibre, SAS.
		// Author: Jerome Brunet <jbrunet@baylibre.com>

		#include <linux/bitfield.h>
		#include <linux/clk.h>
		#include <sound/pcm_params.h>
		#include <sound/pcm_iec958.h>
		#include <sound/soc.h>
		#include <sound/soc-dai.h>

		#include "aiu.h"

		#define AIU_958_MISC_NON_PCM BIT(0)
		#define AIU_958_MISC_MODE_16BITS BIT(1)
		#define AIU_958_MISC_16BITS_ALIGN GENMASK(6, 5)
		#define AIU_958_MISC_MODE_32BITS BIT(7)
		#define AIU_958_MISC_U_FROM_STREAM BIT(12)
		#define AIU_958_MISC_FORCE_LR BIT(13)
		#define AIU_958_CTRL_HOLD_EN BIT(0)
		#define AIU_CLK_CTRL_958_DIV_EN BIT(1)
		#define AIU_CLK_CTRL_958_DIV GENMASK(5, 4)
		#define AIU_CLK_CTRL_958_DIV_MORE BIT(12)

		#define AIU_CS_WORD_LEN 4
		#define AIU_958_INTERNAL_DIV 2

		static void
		aiu_encoder_spdif_divider_enable(struct snd_soc_component *component,
		bool enable)
		{
		snd_soc_component_update_bits(component, AIU_CLK_CTRL,
		AIU_CLK_CTRL_958_DIV_EN,
		enable ? AIU_CLK_CTRL_958_DIV_EN : 0);
		}

		static void aiu_encoder_spdif_hold(struct snd_soc_component *component,
		bool enable)
		{
		snd_soc_component_update_bits(component, AIU_958_CTRL,
		AIU_958_CTRL_HOLD_EN,
		enable ? AIU_958_CTRL_HOLD_EN : 0);
		}

		static int
		aiu_encoder_spdif_trigger(struct snd_pcm_substream *substream, int cmd,
		struct snd_soc_dai *dai)
		{
		struct snd_soc_component *component = dai->component;

		switch (cmd) {
		case SNDRV_PCM_TRIGGER_START:
		case SNDRV_PCM_TRIGGER_RESUME:
		case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
		aiu_encoder_spdif_hold(component, false);
		return 0;

		case SNDRV_PCM_TRIGGER_STOP:
		case SNDRV_PCM_TRIGGER_SUSPEND:
		case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
		aiu_encoder_spdif_hold(component, true);
		return 0;

		default:
		return -EINVAL;
		}
		}

		static int aiu_encoder_spdif_setup_cs_word(struct snd_soc_component *component,
		struct snd_pcm_hw_params *params)
		{
		u8 cs[AIU_CS_WORD_LEN];
		unsigned int val;
		int ret;

		ret = snd_pcm_create_iec958_consumer_hw_params(params, cs,
		AIU_CS_WORD_LEN);
		if (ret < 0)
		return ret;

		/* Write the 1st half word */
		val = cs[1] \| cs[0] << 8;
		snd_soc_component_write(component, AIU_958_CHSTAT_L0, val);
		snd_soc_component_write(component, AIU_958_CHSTAT_R0, val);

		/* Write the 2nd half word */
		val = cs[3] \| cs[2] << 8;
		snd_soc_component_write(component, AIU_958_CHSTAT_L1, val);
		snd_soc_component_write(component, AIU_958_CHSTAT_R1, val);

		return 0;
		}

		static int aiu_encoder_spdif_hw_params(struct snd_pcm_substream *substream,
		struct snd_pcm_hw_params *params,
		struct snd_soc_dai *dai)
		{
		struct snd_soc_component *component = dai->component;
		struct aiu *aiu = snd_soc_component_get_drvdata(component);
		unsigned int val = 0, mrate;
		int ret;

		/* Disable the clock while changing the settings */
		aiu_encoder_spdif_divider_enable(component, false);

		switch (params_physical_width(params)) {
		case 16:
		val \|= AIU_958_MISC_MODE_16BITS;
		val \|= FIELD_PREP(AIU_958_MISC_16BITS_ALIGN, 2);
		break;
		case 32:
		val \|= AIU_958_MISC_MODE_32BITS;
		break;
		default:
		dev_err(dai->dev, "Unsupport physical width\n");
		return -EINVAL;
		}

		snd_soc_component_update_bits(component, AIU_958_MISC,
		AIU_958_MISC_NON_PCM \|
		AIU_958_MISC_MODE_16BITS \|
		AIU_958_MISC_16BITS_ALIGN \|
		AIU_958_MISC_MODE_32BITS \|
		AIU_958_MISC_FORCE_LR \|
		AIU_958_MISC_U_FROM_STREAM,
		val);

		/* Set the stream channel status word */
		ret = aiu_encoder_spdif_setup_cs_word(component, params);
		if (ret) {
		dev_err(dai->dev, "failed to set channel status word\n");
		return ret;
		}

		snd_soc_component_update_bits(component, AIU_CLK_CTRL,
		AIU_CLK_CTRL_958_DIV \|
		AIU_CLK_CTRL_958_DIV_MORE,
		FIELD_PREP(AIU_CLK_CTRL_958_DIV,
		__ffs(AIU_958_INTERNAL_DIV)));

		/* 2 * 32bits per subframe * 2 channels = 128 */
		mrate = params_rate(params) * 128 * AIU_958_INTERNAL_DIV;
		ret = clk_set_rate(aiu->spdif.clks[MCLK].clk, mrate);
		if (ret) {
		dev_err(dai->dev, "failed to set mclk rate\n");
		return ret;
		}

		aiu_encoder_spdif_divider_enable(component, true);

		return 0;
		}

		static int aiu_encoder_spdif_hw_free(struct snd_pcm_substream *substream,
		struct snd_soc_dai *dai)
		{
		struct snd_soc_component *component = dai->component;

		aiu_encoder_spdif_divider_enable(component, false);

		return 0;
		}

		static int aiu_encoder_spdif_startup(struct snd_pcm_substream *substream,
		struct snd_soc_dai *dai)
		{
		struct aiu *aiu = snd_soc_component_get_drvdata(dai->component);
		int ret;

		/*
		* NOTE: Make sure the spdif block is on its own divider.
		*
		* The spdif can be clocked by the i2s master clock or its own
		* clock. We should (in theory) change the source depending on the
		* origin of the data.
		*
		* However, considering the clocking scheme used on these platforms,
		* the master clocks will pick the same PLL source when they are
		* playing from the same FIFO. The clock should be in sync so, it
		* should not be necessary to reparent the spdif master clock.
		*/
		ret = clk_set_parent(aiu->spdif.clks[MCLK].clk,
		aiu->spdif_mclk);
		if (ret)
		return ret;

		ret = clk_bulk_prepare_enable(aiu->spdif.clk_num, aiu->spdif.clks);
		if (ret)
		dev_err(dai->dev, "failed to enable spdif clocks\n");

		return ret;
		}

		static void aiu_encoder_spdif_shutdown(struct snd_pcm_substream *substream,
		struct snd_soc_dai *dai)
		{
		struct aiu *aiu = snd_soc_component_get_drvdata(dai->component);

		clk_bulk_disable_unprepare(aiu->spdif.clk_num, aiu->spdif.clks);
		}

		const struct snd_soc_dai_ops aiu_encoder_spdif_dai_ops = {
		.trigger = aiu_encoder_spdif_trigger,
		.hw_params = aiu_encoder_spdif_hw_params,
		.hw_free = aiu_encoder_spdif_hw_free,
		.startup = aiu_encoder_spdif_startup,
		.shutdown = aiu_encoder_spdif_shutdown,
		};

sound/soc/meson/aiu-fifo-i2s.c

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+153 −0

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		// SPDX-License-Identifier: GPL-2.0
		//
		// Copyright (c) 2020 BayLibre, SAS.
		// Author: Jerome Brunet <jbrunet@baylibre.com>

		#include <linux/bitfield.h>
		#include <linux/clk.h>
		#include <sound/pcm_params.h>
		#include <sound/soc.h>
		#include <sound/soc-dai.h>

		#include "aiu.h"
		#include "aiu-fifo.h"

		#define AIU_I2S_SOURCE_DESC_MODE_8CH BIT(0)
		#define AIU_I2S_SOURCE_DESC_MODE_24BIT BIT(5)
		#define AIU_I2S_SOURCE_DESC_MODE_32BIT BIT(9)
		#define AIU_I2S_SOURCE_DESC_MODE_SPLIT BIT(11)
		#define AIU_MEM_I2S_MASKS_IRQ_BLOCK GENMASK(31, 16)
		#define AIU_MEM_I2S_CONTROL_MODE_16BIT BIT(6)
		#define AIU_MEM_I2S_BUF_CNTL_INIT BIT(0)
		#define AIU_RST_SOFT_I2S_FAST BIT(0)

		#define AIU_FIFO_I2S_BLOCK 256

		static struct snd_pcm_hardware fifo_i2s_pcm = {
		.info = (SNDRV_PCM_INFO_INTERLEAVED \|
		SNDRV_PCM_INFO_MMAP \|
		SNDRV_PCM_INFO_MMAP_VALID \|
		SNDRV_PCM_INFO_PAUSE),
		.formats = AIU_FORMATS,
		.rate_min = 5512,
		.rate_max = 192000,
		.channels_min = 2,
		.channels_max = 8,
		.period_bytes_min = AIU_FIFO_I2S_BLOCK,
		.period_bytes_max = AIU_FIFO_I2S_BLOCK * USHRT_MAX,
		.periods_min = 2,
		.periods_max = UINT_MAX,

		/* No real justification for this */
		.buffer_bytes_max = 1 * 1024 * 1024,
		};

		static int aiu_fifo_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
		struct snd_soc_dai *dai)
		{
		struct snd_soc_component *component = dai->component;
		unsigned int val;

		switch (cmd) {
		case SNDRV_PCM_TRIGGER_START:
		case SNDRV_PCM_TRIGGER_RESUME:
		case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
		snd_soc_component_write(component, AIU_RST_SOFT,
		AIU_RST_SOFT_I2S_FAST);
		snd_soc_component_read(component, AIU_I2S_SYNC, &val);
		break;
		}

		return aiu_fifo_trigger(substream, cmd, dai);
		}

		static int aiu_fifo_i2s_prepare(struct snd_pcm_substream *substream,
		struct snd_soc_dai *dai)
		{
		struct snd_soc_component *component = dai->component;
		int ret;

		ret = aiu_fifo_prepare(substream, dai);
		if (ret)
		return ret;

		snd_soc_component_update_bits(component,
		AIU_MEM_I2S_BUF_CNTL,
		AIU_MEM_I2S_BUF_CNTL_INIT,
		AIU_MEM_I2S_BUF_CNTL_INIT);
		snd_soc_component_update_bits(component,
		AIU_MEM_I2S_BUF_CNTL,
		AIU_MEM_I2S_BUF_CNTL_INIT, 0);

		return 0;
		}

		static int aiu_fifo_i2s_hw_params(struct snd_pcm_substream *substream,
		struct snd_pcm_hw_params *params,
		struct snd_soc_dai *dai)
		{
		struct snd_soc_component *component = dai->component;
		struct aiu_fifo *fifo = dai->playback_dma_data;
		unsigned int val;
		int ret;

		ret = aiu_fifo_hw_params(substream, params, dai);
		if (ret)
		return ret;

		switch (params_physical_width(params)) {
		case 16:
		val = AIU_MEM_I2S_CONTROL_MODE_16BIT;
		break;
		case 32:
		val = 0;
		break;
		default:
		dev_err(dai->dev, "Unsupported physical width %u\n",
		params_physical_width(params));
		return -EINVAL;
		}

		snd_soc_component_update_bits(component, AIU_MEM_I2S_CONTROL,
		AIU_MEM_I2S_CONTROL_MODE_16BIT,
		val);

		/* Setup the irq periodicity */
		val = params_period_bytes(params) / fifo->fifo_block;
		val = FIELD_PREP(AIU_MEM_I2S_MASKS_IRQ_BLOCK, val);
		snd_soc_component_update_bits(component, AIU_MEM_I2S_MASKS,
		AIU_MEM_I2S_MASKS_IRQ_BLOCK, val);

		return 0;
		}

		const struct snd_soc_dai_ops aiu_fifo_i2s_dai_ops = {
		.trigger = aiu_fifo_i2s_trigger,
		.prepare = aiu_fifo_i2s_prepare,
		.hw_params = aiu_fifo_i2s_hw_params,
		.hw_free = aiu_fifo_hw_free,
		.startup = aiu_fifo_startup,
		.shutdown = aiu_fifo_shutdown,
		};

		int aiu_fifo_i2s_dai_probe(struct snd_soc_dai *dai)
		{
		struct snd_soc_component *component = dai->component;
		struct aiu *aiu = snd_soc_component_get_drvdata(component);
		struct aiu_fifo *fifo;
		int ret;

		ret = aiu_fifo_dai_probe(dai);
		if (ret)
		return ret;

		fifo = dai->playback_dma_data;

		fifo->pcm = &fifo_i2s_pcm;
		fifo->mem_offset = AIU_MEM_I2S_START;
		fifo->fifo_block = AIU_FIFO_I2S_BLOCK;
		fifo->pclk = aiu->i2s.clks[PCLK].clk;
		fifo->irq = aiu->i2s.irq;

		return 0;
		}

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