Commit 6ae840e7 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'char-misc-3.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc 

Pull char/misc driver updates from Greg KH:
 "Here's the big char/misc driver update for 3.19-rc1

  Lots of little things all over the place in different drivers, and a
  new subsystem, "coresight" has been added.  Full details are in the
  shortlog"

* tag 'char-misc-3.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc: (73 commits)
  parport: parport_pc, do not remove parent devices early
  spmi: Remove shutdown/suspend/resume kernel-doc
  carma-fpga-program: drop videobuf dependency
  carma-fpga: drop videobuf dependency
  carma-fpga-program.c: fix compile errors
  i8k: Fix temperature bug handling in i8k_get_temp()
  cxl: Name interrupts in /proc/interrupt
  CXL: Return error to PSL if IRQ demultiplexing fails & print clearer warning
  coresight-replicator: remove .owner field for driver
  coresight: fixed comments in coresight.h
  coresight: fix typo in comment in coresight-priv.h
  coresight: bindings for coresight drivers
  coresight: Adding ABI documentation
  w1: support auto-load of w1_bq27000 module.
  w1: avoid potential u16 overflow
  cn: verify msg->len before making callback
  mei: export fw status registers through sysfs
  mei: read and print all six FW status registers
  mei: txe: add cherrytrail device id
  mei: kill cached host and me csr values
  ...
parents e6b5be2b 91905b6f

Documentation/ABI/testing/sysfs-bus-coresight-devices-etb10

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What:		/sys/bus/coresight/devices/<memory_map>.etb/enable_sink

Date:		November 2014

KernelVersion:	3.19

Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>

Description:	(RW) Add/remove a sink from a trace path.  There can be multiple

		source for a single sink.

		ex: echo 1 > /sys/bus/coresight/devices/20010000.etb/enable_sink



What:		/sys/bus/coresight/devices/<memory_map>.etb/status

Date:		November 2014

KernelVersion:	3.19

Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>

Description:	(R) List various control and status registers.  The specific

		layout and content is driver specific.



What:		/sys/bus/coresight/devices/<memory_map>.etb/trigger_cntr

Date:		November 2014

KernelVersion:	3.19

Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>

Description:	(RW) Disables write access to the Trace RAM by stopping the

		formatter after a defined number of words have been stored

		following the trigger event. The number of 32-bit words written

		into the Trace RAM following the trigger event is equal to the

		value stored in this register+1 (from ARM ETB-TRM).

Documentation/ABI/testing/sysfs-bus-coresight-devices-etm3x

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What:		/sys/bus/coresight/devices/<memory_map>.[etm|ptm]/enable_source

Date:		November 2014

KernelVersion:	3.19

Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>

Description:	(RW) Enable/disable tracing on this specific trace entiry.

		Enabling a source implies the source has been configured

		properly and a sink has been identidifed for it.  The path

		of coresight components linking the source to the sink is

		configured and managed automatically by the coresight framework.



What:		/sys/bus/coresight/devices/<memory_map>.[etm|ptm]/status

Date:		November 2014

KernelVersion:	3.19

Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>

Description:	(R) List various control and status registers.  The specific

		layout and content is driver specific.



What:		/sys/bus/coresight/devices/<memory_map>.[etm|ptm]/addr_idx

Date:		November 2014

KernelVersion:	3.19

Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>

Description:	Select which address comparator or pair (of comparators) to

		work with.



What:		/sys/bus/coresight/devices/<memory_map>.[etm|ptm]/addr_acctype

Date:		November 2014

KernelVersion:	3.19

Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>

Description:	(RW) Used in conjunction with @addr_idx.  Specifies

		characteristics about the address comparator being configure,

		for example the access type, the kind of instruction to trace,

		processor contect ID to trigger on, etc.  Individual fields in

		the access type register may vary on the version of the trace

		entity.



What:		/sys/bus/coresight/devices/<memory_map>.[etm|ptm]/addr_range

Date:		November 2014

KernelVersion:	3.19

Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>

Description:	(RW) Used in conjunction with @addr_idx.  Specifies the range of

		addresses to trigger on.  Inclusion or exclusion is specificed

		in the corresponding access type register.



What:		/sys/bus/coresight/devices/<memory_map>.[etm|ptm]/addr_single

Date:		November 2014

KernelVersion:	3.19

Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>

Description:	(RW) Used in conjunction with @addr_idx.  Specifies the single

		address to trigger on, highly influenced by the configuration

		options of the corresponding access type register.



What:		/sys/bus/coresight/devices/<memory_map>.[etm|ptm]/addr_start

Date:		November 2014

KernelVersion:	3.19

Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>

Description:	(RW) Used in conjunction with @addr_idx.  Specifies the single

		address to start tracing on, highly influenced by the

		configuration options of the corresponding access type register.



What:		/sys/bus/coresight/devices/<memory_map>.[etm|ptm]/addr_stop

Date:		November 2014

KernelVersion:	3.19

Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>

Description:	(RW) Used in conjunction with @addr_idx.  Specifies the single

		address to stop tracing on, highly influenced by the

		configuration options of the corresponding access type register.



What:		/sys/bus/coresight/devices/<memory_map>.[etm|ptm]/cntr_idx

Date:		November 2014

KernelVersion:	3.19

Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>

Description:	(RW) Specifies the counter to work on.



What:		/sys/bus/coresight/devices/<memory_map>.[etm|ptm]/cntr_event

Date:		November 2014

KernelVersion:	3.19

Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>

Description: 	(RW) Used in conjunction with cntr_idx, give access to the

		counter event register.



What:		/sys/bus/coresight/devices/<memory_map>.[etm|ptm]/cntr_val

Date:		November 2014

KernelVersion:	3.19

Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>

Description: 	(RW) Used in conjunction with cntr_idx, give access to the

		counter value register.



What:		/sys/bus/coresight/devices/<memory_map>.[etm|ptm]/cntr_rld_val

Date:		November 2014

KernelVersion:	3.19

Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>

Description: 	(RW) Used in conjunction with cntr_idx, give access to the

		counter reload value register.



What:		/sys/bus/coresight/devices/<memory_map>.[etm|ptm]/cntr_rld_event

Date:		November 2014

KernelVersion:	3.19

Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>

Description: 	(RW) Used in conjunction with cntr_idx, give access to the

		counter reload event register.



What:		/sys/bus/coresight/devices/<memory_map>.[etm|ptm]/ctxid_idx

Date:		November 2014

KernelVersion:	3.19

Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>

Description: 	(RW) Specifies the index of the context ID register to be

		selected.



What:		/sys/bus/coresight/devices/<memory_map>.[etm|ptm]/ctxid_mask

Date:		November 2014

KernelVersion:	3.19

Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>

Description: 	(RW) Mask to apply to all the context ID comparator.



What:		/sys/bus/coresight/devices/<memory_map>.[etm|ptm]/ctxid_val

Date:		November 2014

KernelVersion:	3.19

Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>

Description: 	(RW) Used with the ctxid_idx, specify with context ID to trigger

		on.



What:		/sys/bus/coresight/devices/<memory_map>.[etm|ptm]/enable_event

Date:		November 2014

KernelVersion:	3.19

Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>

Description: 	(RW) Defines which event triggers a trace.



What:		/sys/bus/coresight/devices/<memory_map>.[etm|ptm]/etmsr

Date:		November 2014

KernelVersion:	3.19

Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>

Description: 	(RW) Gives access to the ETM status register, which holds

		programming information and status on certains events.



What:		/sys/bus/coresight/devices/<memory_map>.[etm|ptm]/fifofull_level

Date:		November 2014

KernelVersion:	3.19

Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>

Description: 	(RW) Number of byte left in the fifo before considering it full.

		Depending on the tracer's version, can also hold threshold for

		data suppression.



What:		/sys/bus/coresight/devices/<memory_map>.[etm|ptm]/mode

Date:		November 2014

KernelVersion:	3.19

Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>

Description: 	(RW) Interface with the driver's 'mode' field, controlling

		various aspect of the trace entity such as time stamping,

		context ID size and cycle accurate tracing.  Driver specific

		and bound to change depending on the driver.



What:		/sys/bus/coresight/devices/<memory_map>.[etm|ptm]/nr_addr_cmp

Date:		November 2014

KernelVersion:	3.19

Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>

Description: 	(R) Provides the number of address comparators pairs accessible

		on a trace unit, as specified by bit 3:0 of register ETMCCR.



What:		/sys/bus/coresight/devices/<memory_map>.[etm|ptm]/nr_cntr

Date:		November 2014

KernelVersion:	3.19

Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>

Description: 	(R) Provides the number of counters accessible on a trace unit,

		as specified by bit 15:13 of register ETMCCR.



What:		/sys/bus/coresight/devices/<memory_map>.[etm|ptm]/nr_ctxid_cmp

Date:		November 2014

KernelVersion:	3.19

Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>

Description: 	(R) Provides the number of context ID comparator available on a

		trace unit, as specified by bit 25:24 of register ETMCCR.



What:		/sys/bus/coresight/devices/<memory_map>.[etm|ptm]/reset

Date:		November 2014

KernelVersion:	3.19

Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>

Description: 	(W) Cancels all configuration on a trace unit and set it back

		to its boot configuration.



What:		/sys/bus/coresight/devices/<memory_map>.[etm|ptm]/seq_12_event

Date:		November 2014

KernelVersion:	3.19

Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>

Description: 	(RW) Defines the event that causes the sequencer to transition

		from state 1 to state 2.



What:		/sys/bus/coresight/devices/<memory_map>.[etm|ptm]/seq_13_event

Date:		November 2014

KernelVersion:	3.19

Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>

Description: 	(RW) Defines the event that causes the sequencer to transition

		from state 1 to state 3.



What:		/sys/bus/coresight/devices/<memory_map>.[etm|ptm]/seq_21_event

Date:		November 2014

KernelVersion:	3.19

Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>

Description: 	(RW) Defines the event that causes the sequencer to transition

		from state 2 to state 1.



What:		/sys/bus/coresight/devices/<memory_map>.[etm|ptm]/seq_23_event

Date:		November 2014

KernelVersion:	3.19

Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>

Description: 	(RW) Defines the event that causes the sequencer to transition

		from state 2 to state 3.



What:		/sys/bus/coresight/devices/<memory_map>.[etm|ptm]/seq_31_event

Date:		November 2014

KernelVersion:	3.19

Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>

Description: 	(RW) Defines the event that causes the sequencer to transition

		from state 3 to state 1.



What:		/sys/bus/coresight/devices/<memory_map>.[etm|ptm]/seq_32_event

Date:		November 2014

KernelVersion:	3.19

Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>

Description: 	(RW) Defines the event that causes the sequencer to transition

		from state 3 to state 2.



What:		/sys/bus/coresight/devices/<memory_map>.[etm|ptm]/curr_seq_state

Date:		November 2014

KernelVersion:	3.19

Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>

Description: 	(R) Holds the current state of the sequencer.



What:		/sys/bus/coresight/devices/<memory_map>.[etm|ptm]/sync_freq

Date:		November 2014

KernelVersion:	3.19

Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>

Description: 	(RW) Holds the trace synchronization frequency value - must be

		programmed with the various implementation behavior in mind.



What:		/sys/bus/coresight/devices/<memory_map>.[etm|ptm]/timestamp_event

Date:		November 2014

KernelVersion:	3.19

Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>

Description: 	(RW) Defines an event that requests the insertion of a timestamp

		into the trace stream.



What:		/sys/bus/coresight/devices/<memory_map>.[etm|ptm]/traceid

Date:		November 2014

KernelVersion:	3.19

Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>

Description: 	(RW) Holds the trace ID that will appear in the trace stream

		coming from this trace entity.



What:		/sys/bus/coresight/devices/<memory_map>.[etm|ptm]/trigger_event

Date:		November 2014

KernelVersion:	3.19

Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>

Description: 	(RW) Define the event that controls the trigger.

Documentation/ABI/testing/sysfs-bus-coresight-devices-funnel

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What:		/sys/bus/coresight/devices/<memory_map>.funnel/funnel_ctrl

Date:		November 2014

KernelVersion:	3.19

Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>

Description:	(RW) Enables the slave ports and defines the hold time of the

		slave ports.



What:		/sys/bus/coresight/devices/<memory_map>.funnel/priority

Date:		November 2014

KernelVersion:	3.19

Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>

Description:	(RW) Defines input port priority order.

Documentation/ABI/testing/sysfs-bus-coresight-devices-tmc

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What:		/sys/bus/coresight/devices/<memory_map>.tmc/trigger_cntr

Date:		November 2014

KernelVersion:	3.19

Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>

Description:	(RW) Disables write access to the Trace RAM by stopping the

		formatter after a defined number of words have been stored

		following the trigger event. Additional interface for this

		driver are expected to be added as it matures.

Documentation/DocBook/uio-howto.tmpl

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@@ -540,7 +540,7 @@ appears in sysfs. 
</para></listitem>



<listitem><para>

<varname>unsigned long size</varname>: Fill in the size of the

<varname>resource_size_t size</varname>: Fill in the size of the

memory block that <varname>addr</varname> points to. If <varname>size</varname>

is zero, the mapping is considered unused. Note that you

<emphasis>must</emphasis> initialize <varname>size</varname> with zero for

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