Commit 6ae5d1ce authored Feb 14, 2020 by Jani Nikula

drm/i915/csr: use intel_de_*() functions for register access



The implicit "dev_priv" local variable use has been a long-standing pain
point in the register access macros I915_READ(), I915_WRITE(),
POSTING_READ(), I915_READ_FW(), and I915_WRITE_FW().

Replace them with the corresponding new display engine register
accessors intel_de_read(), intel_de_write(), intel_de_posting_read(),
intel_de_read_fw(), and intel_de_write_fw().

No functional changes.

Generated using the following semantic patch:

@@
expression REG, OFFSET;
@@
- I915_READ(REG)
+ intel_de_read(dev_priv, REG)

@@
expression REG, OFFSET;
@@
- POSTING_READ(REG)
+ intel_de_posting_read(dev_priv, REG)

@@
expression REG, OFFSET;
@@
- I915_WRITE(REG, OFFSET)
+ intel_de_write(dev_priv, REG, OFFSET)

@@
expression REG;
@@
- I915_READ_FW(REG)
+ intel_de_read_fw(dev_priv, REG)

@@
expression REG, OFFSET;
@@
- I915_WRITE_FW(REG, OFFSET)
+ intel_de_write_fw(dev_priv, REG, OFFSET)

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200214140910.23194-1-jani.nikula@intel.com

parent 8d6cae6f

drivers/gpu/drm/i915/display/intel_csr.c

+6 −5

Original line number	Diff line number	Diff line
		@@ -27,6 +27,7 @@
		#include "i915_drv.h"
		#include "i915_reg.h"
		#include "intel_csr.h"
		#include "intel_de.h"

		/**
		* DOC: csr support for dmc
		@@ -276,11 +277,11 @@ static void gen9_set_dc_state_debugmask(struct drm_i915_private *dev_priv)
		mask \|= DC_STATE_DEBUG_MASK_CORES;

		/* The below bit doesn't need to be cleared ever afterwards */
		val = I915_READ(DC_STATE_DEBUG);
		val = intel_de_read(dev_priv, DC_STATE_DEBUG);
		if ((val & mask) != mask) {
		val \|= mask;
		I915_WRITE(DC_STATE_DEBUG, val);
		POSTING_READ(DC_STATE_DEBUG);
		intel_de_write(dev_priv, DC_STATE_DEBUG, val);
		intel_de_posting_read(dev_priv, DC_STATE_DEBUG);
		}
		}

		@@ -321,7 +322,7 @@ void intel_csr_load_program(struct drm_i915_private *dev_priv)
		preempt_enable();

		for (i = 0; i < dev_priv->csr.mmio_count; i++) {
		I915_WRITE(dev_priv->csr.mmioaddr[i],
		intel_de_write(dev_priv, dev_priv->csr.mmioaddr[i],
		dev_priv->csr.mmiodata[i]);
		}

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