Commit 6ac94d3a authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus 

Pull MIPS updates from Ralf Baechle:
 "This weeks' round of MIPS bug fixes for 3.18:

   - wire up the bpf syscall
   - fix TLB dump output for R3000 class TLBs
   - fix strnlen_user return value if no NUL character was found.
   - fix build with binutils 2.24.51+.  While there is no binutils 2.25
     release yet, toolchains derived from binutils 2.24.51+ are already
     in common use.
   - the Octeon GPIO code forgot to offline GPIO IRQs.
   - fix build error for XLP.
   - fix possible BUG assertion with EVA for CMA"

* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus:
  MIPS: Fix build with binutils 2.24.51+
  MIPS: R3000: Fix debug output for Virtual page number
  MIPS: Fix strnlen_user() return value in case of overlong strings.
  MIPS: CMA: Do not reserve memory if not required
  MIPS: Wire up bpf syscall.
  MIPS/Xlp: Remove the dead function destroy_irq() to fix build error
  MIPS: Octeon: Make Octeon GPIO IRQ chip CPU hotplug-aware
parents 661b99e9 842dfc11

arch/mips/Makefile

+9 −0
Original line number Diff line number Diff line
@@ -93,6 +93,15 @@ LDFLAGS_vmlinux += -G 0 -static -n -nostdlib 
KBUILD_AFLAGS_MODULE		+= -mlong-calls

KBUILD_CFLAGS_MODULE		+= -mlong-calls



#

# pass -msoft-float to GAS if it supports it.  However on newer binutils

# (specifically newer than 2.24.51.20140728) we then also need to explicitly

# set ".set hardfloat" in all files which manipulate floating point registers.

#

ifneq ($(call as-option,-Wa$(comma)-msoft-float,),)

	cflags-y		+= -DGAS_HAS_SET_HARDFLOAT -Wa,-msoft-float

endif



cflags-y += -ffreestanding



#

arch/mips/cavium-octeon/octeon-irq.c

+2 −0
Original line number Diff line number Diff line
@@ -809,6 +809,7 @@ static struct irq_chip octeon_irq_chip_ciu_gpio_v2 = { 
	.irq_set_type = octeon_irq_ciu_gpio_set_type,

#ifdef CONFIG_SMP

	.irq_set_affinity = octeon_irq_ciu_set_affinity_v2,

	.irq_cpu_offline = octeon_irq_cpu_offline_ciu,

#endif

	.flags = IRQCHIP_SET_TYPE_MASKED,

};
@@ -823,6 +824,7 @@ static struct irq_chip octeon_irq_chip_ciu_gpio = { 
	.irq_set_type = octeon_irq_ciu_gpio_set_type,

#ifdef CONFIG_SMP

	.irq_set_affinity = octeon_irq_ciu_set_affinity,

	.irq_cpu_offline = octeon_irq_cpu_offline_ciu,

#endif

	.flags = IRQCHIP_SET_TYPE_MASKED,

};

arch/mips/include/asm/asmmacro-32.h

+6 −0
Original line number Diff line number Diff line
@@ -13,6 +13,8 @@ 
#include <asm/mipsregs.h>



	.macro	fpu_save_single thread tmp=t0

	.set push

	SET_HARDFLOAT

	cfc1	\tmp,  fcr31

	swc1	$f0,  THREAD_FPR0_LS64(\thread)

	swc1	$f1,  THREAD_FPR1_LS64(\thread)
@@ -47,9 +49,12 @@ 
	swc1	$f30, THREAD_FPR30_LS64(\thread)

	swc1	$f31, THREAD_FPR31_LS64(\thread)

	sw	\tmp, THREAD_FCR31(\thread)

	.set pop

	.endm



	.macro	fpu_restore_single thread tmp=t0

	.set push

	SET_HARDFLOAT

	lw	\tmp, THREAD_FCR31(\thread)

	lwc1	$f0,  THREAD_FPR0_LS64(\thread)

	lwc1	$f1,  THREAD_FPR1_LS64(\thread)
@@ -84,6 +89,7 @@ 
	lwc1	$f30, THREAD_FPR30_LS64(\thread)

	lwc1	$f31, THREAD_FPR31_LS64(\thread)

	ctc1	\tmp, fcr31

	.set pop

	.endm



	.macro	cpu_save_nonscratch thread

arch/mips/include/asm/asmmacro.h

+18 −0
Original line number Diff line number Diff line
@@ -57,6 +57,8 @@ 
#endif /* CONFIG_CPU_MIPSR2 */



	.macro	fpu_save_16even thread tmp=t0

	.set	push

	SET_HARDFLOAT

	cfc1	\tmp, fcr31

	sdc1	$f0,  THREAD_FPR0_LS64(\thread)

	sdc1	$f2,  THREAD_FPR2_LS64(\thread)
@@ -75,11 +77,13 @@ 
	sdc1	$f28, THREAD_FPR28_LS64(\thread)

	sdc1	$f30, THREAD_FPR30_LS64(\thread)

	sw	\tmp, THREAD_FCR31(\thread)

	.set	pop

	.endm



	.macro	fpu_save_16odd thread

	.set	push

	.set	mips64r2

	SET_HARDFLOAT

	sdc1	$f1,  THREAD_FPR1_LS64(\thread)

	sdc1	$f3,  THREAD_FPR3_LS64(\thread)

	sdc1	$f5,  THREAD_FPR5_LS64(\thread)
@@ -110,6 +114,8 @@ 
	.endm



	.macro	fpu_restore_16even thread tmp=t0

	.set	push

	SET_HARDFLOAT

	lw	\tmp, THREAD_FCR31(\thread)

	ldc1	$f0,  THREAD_FPR0_LS64(\thread)

	ldc1	$f2,  THREAD_FPR2_LS64(\thread)
@@ -133,6 +139,7 @@ 
	.macro	fpu_restore_16odd thread

	.set	push

	.set	mips64r2

	SET_HARDFLOAT

	ldc1	$f1,  THREAD_FPR1_LS64(\thread)

	ldc1	$f3,  THREAD_FPR3_LS64(\thread)

	ldc1	$f5,  THREAD_FPR5_LS64(\thread)
@@ -277,6 +284,7 @@ 
	.macro	cfcmsa	rd, cs

	.set	push

	.set	noat

	SET_HARDFLOAT

	.insn

	.word	CFC_MSA_INSN | (\cs << 11)

	move	\rd, $1
@@ -286,6 +294,7 @@ 
	.macro	ctcmsa	cd, rs

	.set	push

	.set	noat

	SET_HARDFLOAT

	move	$1, \rs

	.word	CTC_MSA_INSN | (\cd << 6)

	.set	pop
@@ -294,6 +303,7 @@ 
	.macro	ld_d	wd, off, base

	.set	push

	.set	noat

	SET_HARDFLOAT

	add	$1, \base, \off

	.word	LDD_MSA_INSN | (\wd << 6)

	.set	pop
@@ -302,6 +312,7 @@ 
	.macro	st_d	wd, off, base

	.set	push

	.set	noat

	SET_HARDFLOAT

	add	$1, \base, \off

	.word	STD_MSA_INSN | (\wd << 6)

	.set	pop
@@ -310,6 +321,7 @@ 
	.macro	copy_u_w	rd, ws, n

	.set	push

	.set	noat

	SET_HARDFLOAT

	.insn

	.word	COPY_UW_MSA_INSN | (\n << 16) | (\ws << 11)

	/* move triggers an assembler bug... */
@@ -320,6 +332,7 @@ 
	.macro	copy_u_d	rd, ws, n

	.set	push

	.set	noat

	SET_HARDFLOAT

	.insn

	.word	COPY_UD_MSA_INSN | (\n << 16) | (\ws << 11)

	/* move triggers an assembler bug... */
@@ -330,6 +343,7 @@ 
	.macro	insert_w	wd, n, rs

	.set	push

	.set	noat

	SET_HARDFLOAT

	/* move triggers an assembler bug... */

	or	$1, \rs, zero

	.word	INSERT_W_MSA_INSN | (\n << 16) | (\wd << 6)
@@ -339,6 +353,7 @@ 
	.macro	insert_d	wd, n, rs

	.set	push

	.set	noat

	SET_HARDFLOAT

	/* move triggers an assembler bug... */

	or	$1, \rs, zero

	.word	INSERT_D_MSA_INSN | (\n << 16) | (\wd << 6)
@@ -381,6 +396,7 @@ 
	st_d	31, THREAD_FPR31, \thread

	.set	push

	.set	noat

	SET_HARDFLOAT

	cfcmsa	$1, MSA_CSR

	sw	$1, THREAD_MSA_CSR(\thread)

	.set	pop
@@ -389,6 +405,7 @@ 
	.macro	msa_restore_all	thread

	.set	push

	.set	noat

	SET_HARDFLOAT

	lw	$1, THREAD_MSA_CSR(\thread)

	ctcmsa	MSA_CSR, $1

	.set	pop
@@ -441,6 +458,7 @@ 
	.macro	msa_init_all_upper

	.set	push

	.set	noat

	SET_HARDFLOAT

	not	$1, zero

	msa_init_upper	0

	.set	pop

arch/mips/include/asm/fpregdef.h

+14 −0
Original line number Diff line number Diff line
@@ -14,6 +14,20 @@ 


#include <asm/sgidefs.h>



/*

 * starting with binutils 2.24.51.20140729, MIPS binutils warn about mixing

 * hardfloat and softfloat object files.  The kernel build uses soft-float by

 * default, so we also need to pass -msoft-float along to GAS if it supports it.

 * But this in turn causes assembler errors in files which access hardfloat

 * registers.  We detect if GAS supports "-msoft-float" in the Makefile and

 * explicitly put ".set hardfloat" where floating point registers are touched.

 */

#ifdef GAS_HAS_SET_HARDFLOAT

#define SET_HARDFLOAT .set hardfloat

#else

#define SET_HARDFLOAT

#endif



#if _MIPS_SIM == _MIPS_SIM_ABI32



/*

CRA Git | Maintained and supported by SUSTech CRA and CCSE