Commit 6a7e7122 authored by Dinh Nguyen's avatar Dinh Nguyen Committed by Mike Turquette
Browse files

clk: socfpga: Map the clk manager base address in the clock driver 



The clk manager's base address was being mapped in SOCFPGA's arch code and
being extern'ed out to the clock driver. This method is not correct, and the
arch code was not really doing anything with that clk manager anyways.

This patch moves the mapping of the clk manager's base address in the clock
driver itself. Cleans up CLK_OF_DECLARE() into a single registration of all
the clocks.

Suggested-by: default avatarArnd Bergmann <arnd@arndb.de>
Signed-off-by: default avatarDinh Nguyen <dinguyen@altera.com>
Acked-by: default avatarArnd Bergmann <arnd@arndb.de>
---
v2: Use a static declaration for the clk_mgr_base_addr. Clean up the
    CLK_OF_DECLARE() as suggested by Arnd.
parent 6d0abeca

arch/arm/mach-socfpga/socfpga.c

+0 −4
Original line number Diff line number Diff line
@@ -29,7 +29,6 @@ 
void __iomem *socfpga_scu_base_addr = ((void __iomem *)(SOCFPGA_SCU_VIRT_BASE));

void __iomem *sys_manager_base_addr;

void __iomem *rst_manager_base_addr;

void __iomem *clk_mgr_base_addr;

unsigned long cpu1start_addr;



static struct map_desc scu_io_desc __initdata = {
@@ -78,9 +77,6 @@ void __init socfpga_sysmgr_init(void) 


	np = of_find_compatible_node(NULL, NULL, "altr,rst-mgr");

	rst_manager_base_addr = of_iomap(np, 0);



	np = of_find_compatible_node(NULL, NULL, "altr,clk-mgr");

	clk_mgr_base_addr = of_iomap(np, 0);

}



static void __init socfpga_init_irq(void)

drivers/clk/socfpga/clk.c

+16 −4
Original line number Diff line number Diff line
@@ -22,6 +22,7 @@ 
#include <linux/clk-provider.h>

#include <linux/io.h>

#include <linux/of.h>

#include <linux/of_address.h>



/* Clock Manager offsets */

#define CLKMGR_CTRL	0x0
@@ -55,7 +56,7 @@ 
#define div_mask(width)	((1 << (width)) - 1)

#define streq(a, b) (strcmp((a), (b)) == 0)



extern void __iomem *clk_mgr_base_addr;

static void __iomem *clk_mgr_base_addr;



struct socfpga_clk {

	struct clk_gate hw;
@@ -320,19 +321,30 @@ static void __init socfpga_pll_init(struct device_node *node) 
{

	socfpga_clk_init(node, &clk_pll_ops);

}

CLK_OF_DECLARE(socfpga_pll, "altr,socfpga-pll-clock", socfpga_pll_init);



static void __init socfpga_periph_init(struct device_node *node)

{

	socfpga_clk_init(node, &periclk_ops);

}

CLK_OF_DECLARE(socfpga_periph, "altr,socfpga-perip-clk", socfpga_periph_init);



static void __init socfpga_gate_init(struct device_node *node)

{

	socfpga_gate_clk_init(node, &gateclk_ops);

}

CLK_OF_DECLARE(socfpga_gate, "altr,socfpga-gate-clk", socfpga_gate_init);



static struct of_device_id socfpga_child_clocks[] = {

	{ .compatible = "altr,socfpga-pll-clock", socfpga_pll_init, },

	{ .compatible = "altr,socfpga-perip-clk", socfpga_periph_init, },

	{ .compatible = "altr,socfpga-gate-clk", socfpga_gate_init, },

	{},

};



static void __init socfpga_clkmgr_init(struct device_node *node)

{

	clk_mgr_base_addr = of_iomap(node, 0);

	of_clk_init(socfpga_child_clocks);

}

CLK_OF_DECLARE(socfpga_mgr, "altr,clk-mgr", socfpga_clkmgr_init);



void __init socfpga_init_clocks(void)

{

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