drm/amdgpu: add psp_v12_0 for renoir (v2) (6a7a0bdb) · Commits · 戴 / test

drivers/gpu/drm/amd/amdgpu/Makefile

+2 −1

Original line number	Diff line number	Diff line
		@@ -100,7 +100,8 @@ amdgpu-y += \
		amdgpu_psp.o \
		psp_v3_1.o \
		psp_v10_0.o \
		psp_v11_0.o
		psp_v11_0.o \
		psp_v12_0.o

		# add SMC block
		amdgpu-y += \

drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c

+13 −0

Original line number	Diff line number	Diff line
		@@ -32,6 +32,7 @@
		#include "psp_v3_1.h"
		#include "psp_v10_0.h"
		#include "psp_v11_0.h"
		#include "psp_v12_0.h"

		static void psp_set_funcs(struct amdgpu_device *adev);

		@@ -63,6 +64,9 @@ static int psp_early_init(void *handle)
		psp_v11_0_set_psp_funcs(psp);
		psp->autoload_supported = true;
		break;
		case CHIP_RENOIR:
		psp_v12_0_set_psp_funcs(psp);
		break;
		default:
		return -EINVAL;
		}
		@@ -1358,3 +1362,12 @@ const struct amdgpu_ip_block_version psp_v11_0_ip_block =
		.rev = 0,
		.funcs = &psp_ip_funcs,
		};

		const struct amdgpu_ip_block_version psp_v12_0_ip_block =
		{
		.type = AMD_IP_BLOCK_TYPE_PSP,
		.major = 12,
		.minor = 0,
		.rev = 0,
		.funcs = &psp_ip_funcs,
		};

drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h

+1 −0

Original line number	Diff line number	Diff line
		@@ -270,6 +270,7 @@ extern int psp_wait_for(struct psp_context *psp, uint32_t reg_index,
		uint32_t field_val, uint32_t mask, bool check_changed);

		extern const struct amdgpu_ip_block_version psp_v10_0_ip_block;
		extern const struct amdgpu_ip_block_version psp_v12_0_ip_block;

		int psp_gpu_reset(struct amdgpu_device *adev);
		int psp_update_vcn_sram(struct amdgpu_device *adev, int inst_idx,

drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c

+6 −1

Original line number	Diff line number	Diff line
		@@ -368,8 +368,13 @@ amdgpu_ucode_get_load_type(struct amdgpu_device *adev, int load_type)
		else
		return AMDGPU_FW_LOAD_PSP;
		case CHIP_ARCTURUS:
		return AMDGPU_FW_LOAD_DIRECT;
		case CHIP_RENOIR:
		if (load_type == AMDGPU_FW_LOAD_PSP)
		return AMDGPU_FW_LOAD_PSP;
		else
		return AMDGPU_FW_LOAD_DIRECT;

		default:
		DRM_ERROR("Unknown firmware load type\n");
		}

drivers/gpu/drm/amd/amdgpu/psp_v12_0.c

0 → 100644

+565 −0

Original line number	Diff line number	Diff line
		/*
		* Copyright 2019 Advanced Micro Devices, Inc.
		*
		* Permission is hereby granted, free of charge, to any person obtaining a
		* copy of this software and associated documentation files (the "Software"),
		* to deal in the Software without restriction, including without limitation
		* the rights to use, copy, modify, merge, publish, distribute, sublicense,
		* and/or sell copies of the Software, and to permit persons to whom the
		* Software is furnished to do so, subject to the following conditions:
		*
		* The above copyright notice and this permission notice shall be included in
		* all copies or substantial portions of the Software.
		*
		* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
		* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
		* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
		* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
		* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
		* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
		* OTHER DEALINGS IN THE SOFTWARE.
		*/

		#include <linux/firmware.h>
		#include "amdgpu.h"
		#include "amdgpu_psp.h"
		#include "amdgpu_ucode.h"
		#include "soc15_common.h"
		#include "psp_v12_0.h"

		#include "mp/mp_12_0_0_offset.h"
		#include "mp/mp_12_0_0_sh_mask.h"
		#include "gc/gc_9_0_offset.h"
		#include "sdma0/sdma0_4_0_offset.h"
		#include "nbio/nbio_7_4_offset.h"

		#include "oss/osssys_4_0_offset.h"
		#include "oss/osssys_4_0_sh_mask.h"

		MODULE_FIRMWARE("amdgpu/renoir_asd.bin");
		/* address block */
		#define smnMP1_FIRMWARE_FLAGS 0x3010024

		static int psp_v12_0_init_microcode(struct psp_context *psp)
		{
		struct amdgpu_device *adev = psp->adev;
		const char *chip_name;
		char fw_name[30];
		int err = 0;
		const struct psp_firmware_header_v1_0 *asd_hdr;

		DRM_DEBUG("\n");

		switch (adev->asic_type) {
		case CHIP_RENOIR:
		chip_name = "renoir";
		break;
		default:
		BUG();
		}

		snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name);
		err = request_firmware(&adev->psp.asd_fw, fw_name, adev->dev);
		if (err)
		goto out1;

		err = amdgpu_ucode_validate(adev->psp.asd_fw);
		if (err)
		goto out1;

		asd_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data;
		adev->psp.asd_fw_version = le32_to_cpu(asd_hdr->header.ucode_version);
		adev->psp.asd_feature_version = le32_to_cpu(asd_hdr->ucode_feature_version);
		adev->psp.asd_ucode_size = le32_to_cpu(asd_hdr->header.ucode_size_bytes);
		adev->psp.asd_start_addr = (uint8_t *)asd_hdr +
		le32_to_cpu(asd_hdr->header.ucode_array_offset_bytes);

		return 0;

		out1:
		release_firmware(adev->psp.asd_fw);
		adev->psp.asd_fw = NULL;

		return err;
		}

		static int psp_v12_0_bootloader_load_sysdrv(struct psp_context *psp)
		{
		int ret;
		uint32_t psp_gfxdrv_command_reg = 0;
		struct amdgpu_device *adev = psp->adev;
		uint32_t sol_reg;

		/* Check sOS sign of life register to confirm sys driver and sOS
		* are already been loaded.
		*/
		sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
		if (sol_reg) {
		psp->sos_fw_version = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_58);
		printk("sos fw version = 0x%x.\n", psp->sos_fw_version);
		return 0;
		}

		/* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */
		ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
		0x80000000, 0x80000000, false);
		if (ret)
		return ret;

		memset(psp->fw_pri_buf, 0, PSP_1_MEG);

		/* Copy PSP System Driver binary to memory */
		memcpy(psp->fw_pri_buf, psp->sys_start_addr, psp->sys_bin_size);

		/* Provide the sys driver to bootloader */
		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
		(uint32_t)(psp->fw_pri_mc_addr >> 20));
		psp_gfxdrv_command_reg = 1 << 16;
		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
		psp_gfxdrv_command_reg);

		/* there might be handshake issue with hardware which needs delay */
		mdelay(20);

		ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
		0x80000000, 0x80000000, false);

		return ret;
		}

		static int psp_v12_0_bootloader_load_sos(struct psp_context *psp)
		{
		int ret;
		unsigned int psp_gfxdrv_command_reg = 0;
		struct amdgpu_device *adev = psp->adev;
		uint32_t sol_reg;

		/* Check sOS sign of life register to confirm sys driver and sOS
		* are already been loaded.
		*/
		sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
		if (sol_reg)
		return 0;

		/* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */
		ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
		0x80000000, 0x80000000, false);
		if (ret)
		return ret;

		memset(psp->fw_pri_buf, 0, PSP_1_MEG);

		/* Copy Secure OS binary to PSP memory */
		memcpy(psp->fw_pri_buf, psp->sos_start_addr, psp->sos_bin_size);

		/* Provide the PSP secure OS to bootloader */
		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
		(uint32_t)(psp->fw_pri_mc_addr >> 20));
		psp_gfxdrv_command_reg = 2 << 16;
		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
		psp_gfxdrv_command_reg);

		/* there might be handshake issue with hardware which needs delay */
		mdelay(20);
		ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81),
		RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81),
		0, true);

		return ret;
		}

		static void psp_v12_0_reroute_ih(struct psp_context *psp)
		{
		struct amdgpu_device *adev = psp->adev;
		uint32_t tmp;

		/* Change IH ring for VMC */
		tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1244b);
		tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, CLIENT_TYPE, 1);
		tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1);

		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 3);
		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp);
		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET);

		mdelay(20);
		psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
		0x80000000, 0x8000FFFF, false);

		/* Change IH ring for UMC */
		tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1216b);
		tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1);

		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 4);
		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp);
		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET);

		mdelay(20);
		psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
		0x80000000, 0x8000FFFF, false);
		}

		static int psp_v12_0_ring_init(struct psp_context *psp,
		enum psp_ring_type ring_type)
		{
		int ret = 0;
		struct psp_ring *ring;
		struct amdgpu_device *adev = psp->adev;

		psp_v12_0_reroute_ih(psp);

		ring = &psp->km_ring;

		ring->ring_type = ring_type;

		/* allocate 4k Page of Local Frame Buffer memory for ring */
		ring->ring_size = 0x1000;
		ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE,
		AMDGPU_GEM_DOMAIN_VRAM,
		&adev->firmware.rbuf,
		&ring->ring_mem_mc_addr,
		(void **)&ring->ring_mem);
		if (ret) {
		ring->ring_size = 0;
		return ret;
		}

		return 0;
		}

		static bool psp_v12_0_support_vmr_ring(struct psp_context *psp)
		{
		if (amdgpu_sriov_vf(psp->adev) && psp->sos_fw_version > 0x80045)
		return true;
		return false;
		}

		static int psp_v12_0_ring_create(struct psp_context *psp,
		enum psp_ring_type ring_type)
		{
		int ret = 0;
		unsigned int psp_ring_reg = 0;
		struct psp_ring *ring = &psp->km_ring;
		struct amdgpu_device *adev = psp->adev;

		if (psp_v12_0_support_vmr_ring(psp)) {
		/* Write low address of the ring to C2PMSG_102 */
		psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_ring_reg);
		/* Write high address of the ring to C2PMSG_103 */
		psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_103, psp_ring_reg);

		/* Write the ring initialization command to C2PMSG_101 */
		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
		GFX_CTRL_CMD_ID_INIT_GPCOM_RING);

		/* there might be handshake issue with hardware which needs delay */
		mdelay(20);

		/* Wait for response flag (bit 31) in C2PMSG_101 */
		ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
		0x80000000, 0x8000FFFF, false);

		} else {
		/* Write low address of the ring to C2PMSG_69 */
		psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg);
		/* Write high address of the ring to C2PMSG_70 */
		psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg);
		/* Write size of ring to C2PMSG_71 */
		psp_ring_reg = ring->ring_size;
		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg);
		/* Write the ring initialization command to C2PMSG_64 */
		psp_ring_reg = ring_type;
		psp_ring_reg = psp_ring_reg << 16;
		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg);

		/* there might be handshake issue with hardware which needs delay */
		mdelay(20);

		/* Wait for response flag (bit 31) in C2PMSG_64 */
		ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
		0x80000000, 0x8000FFFF, false);
		}

		return ret;
		}

		static int psp_v12_0_ring_stop(struct psp_context *psp,
		enum psp_ring_type ring_type)
		{
		int ret = 0;
		struct amdgpu_device *adev = psp->adev;

		/* Write the ring destroy command*/
		if (psp_v12_0_support_vmr_ring(psp))
		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
		GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING);
		else
		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64,
		GFX_CTRL_CMD_ID_DESTROY_RINGS);

		/* there might be handshake issue with hardware which needs delay */
		mdelay(20);

		/* Wait for response flag (bit 31) */
		if (psp_v12_0_support_vmr_ring(psp))
		ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
		0x80000000, 0x80000000, false);
		else
		ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
		0x80000000, 0x80000000, false);

		return ret;
		}

		static int psp_v12_0_ring_destroy(struct psp_context *psp,
		enum psp_ring_type ring_type)
		{
		int ret = 0;
		struct psp_ring *ring = &psp->km_ring;
		struct amdgpu_device *adev = psp->adev;

		ret = psp_v12_0_ring_stop(psp, ring_type);
		if (ret)
		DRM_ERROR("Fail to stop psp ring\n");

		amdgpu_bo_free_kernel(&adev->firmware.rbuf,
		&ring->ring_mem_mc_addr,
		(void **)&ring->ring_mem);

		return ret;
		}

		static int psp_v12_0_cmd_submit(struct psp_context *psp,
		struct amdgpu_firmware_info *ucode,
		uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr,
		int index)
		{
		unsigned int psp_write_ptr_reg = 0;
		struct psp_gfx_rb_frame *write_frame = psp->km_ring.ring_mem;
		struct psp_ring *ring = &psp->km_ring;
		struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem;
		struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start +
		ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1;
		struct amdgpu_device *adev = psp->adev;
		uint32_t ring_size_dw = ring->ring_size / 4;
		uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4;

		/* KM (GPCOM) prepare write pointer */
		if (psp_v12_0_support_vmr_ring(psp))
		psp_write_ptr_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102);
		else
		psp_write_ptr_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);

		/* Update KM RB frame pointer to new frame */
		/* write_frame ptr increments by size of rb_frame in bytes */
		/* psp_write_ptr_reg increments by size of rb_frame in DWORDs */
		if ((psp_write_ptr_reg % ring_size_dw) == 0)
		write_frame = ring_buffer_start;
		else
		write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw);
		/* Check invalid write_frame ptr address */
		if ((write_frame < ring_buffer_start) \|\| (ring_buffer_end < write_frame)) {
		DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n",
		ring_buffer_start, ring_buffer_end, write_frame);
		DRM_ERROR("write_frame is pointing to address out of bounds\n");
		return -EINVAL;
		}

		/* Initialize KM RB frame */
		memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame));

		/* Update KM RB frame */
		write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr);
		write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr);
		write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr);
		write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr);
		write_frame->fence_value = index;

		/* Update the write Pointer in DWORDs */
		psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw;
		if (psp_v12_0_support_vmr_ring(psp)) {
		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_write_ptr_reg);
		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, GFX_CTRL_CMD_ID_CONSUME_CMD);
		} else
		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, psp_write_ptr_reg);

		return 0;
		}

		static int
		psp_v12_0_sram_map(struct amdgpu_device *adev,
		unsigned int sram_offset, unsigned int sram_addr_reg_offset,
		unsigned int *sram_data_reg_offset,
		enum AMDGPU_UCODE_ID ucode_id)
		{
		int ret = 0;

		switch (ucode_id) {
		/* TODO: needs to confirm */
		#if 0
		case AMDGPU_UCODE_ID_SMC:
		*sram_offset = 0;
		*sram_addr_reg_offset = 0;
		*sram_data_reg_offset = 0;
		break;
		#endif

		case AMDGPU_UCODE_ID_CP_CE:
		*sram_offset = 0x0;
		*sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_ADDR);
		*sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_DATA);
		break;

		case AMDGPU_UCODE_ID_CP_PFP:
		*sram_offset = 0x0;
		*sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_ADDR);
		*sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_DATA);
		break;

		case AMDGPU_UCODE_ID_CP_ME:
		*sram_offset = 0x0;
		*sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_ADDR);
		*sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_DATA);
		break;

		case AMDGPU_UCODE_ID_CP_MEC1:
		*sram_offset = 0x10000;
		*sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_ADDR);
		*sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_DATA);
		break;

		case AMDGPU_UCODE_ID_CP_MEC2:
		*sram_offset = 0x10000;
		*sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_ADDR);
		*sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_DATA);
		break;

		case AMDGPU_UCODE_ID_RLC_G:
		*sram_offset = 0x2000;
		*sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_ADDR);
		*sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_DATA);
		break;

		case AMDGPU_UCODE_ID_SDMA0:
		*sram_offset = 0x0;
		*sram_addr_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_ADDR);
		*sram_data_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_DATA);
		break;

		/* TODO: needs to confirm */
		#if 0
		case AMDGPU_UCODE_ID_SDMA1:
		*sram_offset = ;
		*sram_addr_reg_offset = ;
		break;

		case AMDGPU_UCODE_ID_UVD:
		*sram_offset = ;
		*sram_addr_reg_offset = ;
		break;

		case AMDGPU_UCODE_ID_VCE:
		*sram_offset = ;
		*sram_addr_reg_offset = ;
		break;
		#endif

		case AMDGPU_UCODE_ID_MAXIMUM:
		default:
		ret = -EINVAL;
		break;
		}

		return ret;
		}

		static bool psp_v12_0_compare_sram_data(struct psp_context *psp,
		struct amdgpu_firmware_info *ucode,
		enum AMDGPU_UCODE_ID ucode_type)
		{
		int err = 0;
		unsigned int fw_sram_reg_val = 0;
		unsigned int fw_sram_addr_reg_offset = 0;
		unsigned int fw_sram_data_reg_offset = 0;
		unsigned int ucode_size;
		uint32_t *ucode_mem = NULL;
		struct amdgpu_device *adev = psp->adev;

		err = psp_v12_0_sram_map(adev, &fw_sram_reg_val, &fw_sram_addr_reg_offset,
		&fw_sram_data_reg_offset, ucode_type);
		if (err)
		return false;

		WREG32(fw_sram_addr_reg_offset, fw_sram_reg_val);

		ucode_size = ucode->ucode_size;
		ucode_mem = (uint32_t *)ucode->kaddr;
		while (ucode_size) {
		fw_sram_reg_val = RREG32(fw_sram_data_reg_offset);

		if (*ucode_mem != fw_sram_reg_val)
		return false;

		ucode_mem++;
		/* 4 bytes */
		ucode_size -= 4;
		}

		return true;
		}

		static int psp_v12_0_mode1_reset(struct psp_context *psp)
		{
		int ret;
		uint32_t offset;
		struct amdgpu_device *adev = psp->adev;

		offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64);

		ret = psp_wait_for(psp, offset, 0x80000000, 0x8000FFFF, false);

		if (ret) {
		DRM_INFO("psp is not working correctly before mode1 reset!\n");
		return -EINVAL;
		}

		/send the mode 1 reset command/
		WREG32(offset, GFX_CTRL_CMD_ID_MODE1_RST);

		msleep(500);

		offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_33);

		ret = psp_wait_for(psp, offset, 0x80000000, 0x80000000, false);

		if (ret) {
		DRM_INFO("psp mode 1 reset failed!\n");
		return -EINVAL;
		}

		DRM_INFO("psp mode1 reset succeed \n");

		return 0;
		}

		static const struct psp_funcs psp_v12_0_funcs = {
		.init_microcode = psp_v12_0_init_microcode,
		.bootloader_load_sysdrv = psp_v12_0_bootloader_load_sysdrv,
		.bootloader_load_sos = psp_v12_0_bootloader_load_sos,
		.ring_init = psp_v12_0_ring_init,
		.ring_create = psp_v12_0_ring_create,
		.ring_stop = psp_v12_0_ring_stop,
		.ring_destroy = psp_v12_0_ring_destroy,
		.cmd_submit = psp_v12_0_cmd_submit,
		.compare_sram_data = psp_v12_0_compare_sram_data,
		.mode1_reset = psp_v12_0_mode1_reset,
		};

		void psp_v12_0_set_psp_funcs(struct psp_context *psp)
		{
		psp->funcs = &psp_v12_0_funcs;
		}

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