Commit 6a549b9f authored by Jose Abreu's avatar Jose Abreu Committed by Jakub Kicinski
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net: stmmac: xgmac: Add TBS support 



Adds all the necessary HW hooks to support TBS feature in XGMAC cores.

Changes from v1:
- Remove unneeded LT shift as the IP already does this.

Signed-off-by: default avatarJose Abreu <Jose.Abreu@synopsys.com>
Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parent 430b383c

drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h

+13 −0
Original line number Diff line number Diff line
@@ -139,6 +139,7 @@ 
#define XGMAC_HWFEAT_TXQCNT		GENMASK(9, 6)

#define XGMAC_HWFEAT_RXQCNT		GENMASK(3, 0)

#define XGMAC_HW_FEATURE3		0x00000128

#define XGMAC_HWFEAT_TBSSEL		BIT(27)

#define XGMAC_HWFEAT_FPESEL		BIT(26)

#define XGMAC_HWFEAT_ESTWID		GENMASK(24, 23)

#define XGMAC_HWFEAT_ESTDEP		GENMASK(22, 20)
@@ -346,6 +347,13 @@ 
#define XGMAC_TDPS			GENMASK(29, 0)

#define XGMAC_RX_EDMA_CTRL		0x00003044

#define XGMAC_RDPS			GENMASK(29, 0)

#define XGMAC_DMA_TBS_CTRL0		0x00003054

#define XGMAC_DMA_TBS_CTRL1		0x00003058

#define XGMAC_DMA_TBS_CTRL2		0x0000305c

#define XGMAC_DMA_TBS_CTRL3		0x00003060

#define XGMAC_FTOS			GENMASK(31, 8)

#define XGMAC_FTOV			BIT(0)

#define XGMAC_DEF_FTOS			(XGMAC_FTOS | XGMAC_FTOV)

#define XGMAC_DMA_SAFETY_INT_STATUS	0x00003064

#define XGMAC_MCSIS			BIT(31)

#define XGMAC_MSUIS			BIT(29)
@@ -360,6 +368,7 @@ 
#define XGMAC_SPH			BIT(24)

#define XGMAC_PBLx8			BIT(16)

#define XGMAC_DMA_CH_TX_CONTROL(x)	(0x00003104 + (0x80 * (x)))

#define XGMAC_EDSE			BIT(28)

#define XGMAC_TxPBL			GENMASK(21, 16)

#define XGMAC_TxPBL_SHIFT		16

#define XGMAC_TSE			BIT(12)
@@ -404,6 +413,9 @@ 
#define XGMAC_REGSIZE			((0x0000317c + (0x80 * 15)) / 4)



/* Descriptors */

#define XGMAC_TDES0_LTV			BIT(31)

#define XGMAC_TDES0_LT			GENMASK(7, 0)

#define XGMAC_TDES1_LT			GENMASK(31, 8)

#define XGMAC_TDES2_IVT			GENMASK(31, 16)

#define XGMAC_TDES2_IVT_SHIFT		16

#define XGMAC_TDES2_IOC			BIT(31)
@@ -422,6 +434,7 @@ 
#define XGMAC_TDES3_TCMSSV		BIT(26)

#define XGMAC_TDES3_SAIC		GENMASK(25, 23)

#define XGMAC_TDES3_SAIC_SHIFT		23

#define XGMAC_TDES3_TBSV		BIT(24)

#define XGMAC_TDES3_THL			GENMASK(22, 19)

#define XGMAC_TDES3_THL_SHIFT		19

#define XGMAC_TDES3_IVTIR		GENMASK(19, 18)

drivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c

+9 −0
Original line number Diff line number Diff line
@@ -339,6 +339,14 @@ static void dwxgmac2_set_vlan(struct dma_desc *p, u32 type) 
	p->des2 |= cpu_to_le32(type & XGMAC_TDES2_VTIR);

}



static void dwxgmac2_set_tbs(struct dma_edesc *p, u32 sec, u32 nsec)

{

	p->des4 = cpu_to_le32((sec & XGMAC_TDES0_LT) | XGMAC_TDES0_LTV);

	p->des5 = cpu_to_le32(nsec & XGMAC_TDES1_LT);

	p->des6 = 0;

	p->des7 = 0;

}



const struct stmmac_desc_ops dwxgmac210_desc_ops = {

	.tx_status = dwxgmac2_get_tx_status,

	.rx_status = dwxgmac2_get_rx_status,
@@ -368,4 +376,5 @@ const struct stmmac_desc_ops dwxgmac210_desc_ops = { 
	.set_sarc = dwxgmac2_set_sarc,

	.set_vlan_tag = dwxgmac2_set_vlan_tag,

	.set_vlan = dwxgmac2_set_vlan,

	.set_tbs = dwxgmac2_set_tbs,

};

drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c

+24 −0
Original line number Diff line number Diff line
@@ -429,6 +429,7 @@ static void dwxgmac2_get_hw_feature(void __iomem *ioaddr, 


	/* MAC HW feature 3 */

	hw_cap = readl(ioaddr + XGMAC_HW_FEATURE3);

	dma_cap->tbssel = (hw_cap & XGMAC_HWFEAT_TBSSEL) >> 27;

	dma_cap->fpesel = (hw_cap & XGMAC_HWFEAT_FPESEL) >> 26;

	dma_cap->estwid = (hw_cap & XGMAC_HWFEAT_ESTWID) >> 23;

	dma_cap->estdep = (hw_cap & XGMAC_HWFEAT_ESTDEP) >> 20;
@@ -523,6 +524,28 @@ static void dwxgmac2_enable_sph(void __iomem *ioaddr, bool en, u32 chan) 
	writel(value, ioaddr + XGMAC_DMA_CH_CONTROL(chan));

}



static int dwxgmac2_enable_tbs(void __iomem *ioaddr, bool en, u32 chan)

{

	u32 value = readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));



	if (en)

		value |= XGMAC_EDSE;

	else

		value &= ~XGMAC_EDSE;



	writel(value, ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));



	value = readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan)) & XGMAC_EDSE;

	if (en && !value)

		return -EIO;



	writel(XGMAC_DEF_FTOS, ioaddr + XGMAC_DMA_TBS_CTRL0);

	writel(XGMAC_DEF_FTOS, ioaddr + XGMAC_DMA_TBS_CTRL1);

	writel(XGMAC_DEF_FTOS, ioaddr + XGMAC_DMA_TBS_CTRL2);

	writel(XGMAC_DEF_FTOS, ioaddr + XGMAC_DMA_TBS_CTRL3);

	return 0;

}



const struct stmmac_dma_ops dwxgmac210_dma_ops = {

	.reset = dwxgmac2_dma_reset,

	.init = dwxgmac2_dma_init,
@@ -550,4 +573,5 @@ const struct stmmac_dma_ops dwxgmac210_dma_ops = { 
	.qmode = dwxgmac2_qmode,

	.set_bfsize = dwxgmac2_set_bfsize,

	.enable_sph = dwxgmac2_enable_sph,

	.enable_tbs = dwxgmac2_enable_tbs,

};

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