Commit 6a505e64 authored by Chris Wilson's avatar Chris Wilson
Browse files

drm/i915/gt: Include a bunch more rcs image state 



Empirically the minimal context image we use for rcs is insufficient to
state the engine. This is demonstrated if we poison the context image
such that any uninitialised state is invalid, and so if the engine
samples beyond our defined region, will fail to start.

Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: default avatarMika Kuoppala <mika.kuoppala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200102131707.1463945-1-chris@chris-wilson.co.uk
parent 25e8a383

drivers/gpu/drm/i915/gt/intel_lrc.c

+87 −1
Original line number Diff line number Diff line
@@ -492,7 +492,7 @@ static u32 *set_offsets(u32 *regs, 
			const u8 *data,

			const struct intel_engine_cs *engine)

#define NOP(x) (BIT(7) | (x))

#define LRI(count, flags) ((flags) << 6 | (count))

#define LRI(count, flags) ((flags) << 6 | (count) | BUILD_BUG_ON_ZERO(count >= BIT(6)))

#define POSTED BIT(0)

#define REG(x) (((x) >> 2) | BUILD_BUG_ON_ZERO(x >= 0x200))

#define REG16(x) \
@@ -728,6 +728,90 @@ static const u8 gen8_rcs_offsets[] = { 
	END(),

};



static const u8 gen9_rcs_offsets[] = {

	NOP(1),

	LRI(14, POSTED),

	REG16(0x244),

	REG(0x34),

	REG(0x30),

	REG(0x38),

	REG(0x3c),

	REG(0x168),

	REG(0x140),

	REG(0x110),

	REG(0x11c),

	REG(0x114),

	REG(0x118),

	REG(0x1c0),

	REG(0x1c4),

	REG(0x1c8),



	NOP(3),

	LRI(9, POSTED),

	REG16(0x3a8),

	REG16(0x28c),

	REG16(0x288),

	REG16(0x284),

	REG16(0x280),

	REG16(0x27c),

	REG16(0x278),

	REG16(0x274),

	REG16(0x270),



	NOP(13),

	LRI(1, 0),

	REG(0xc8),



	NOP(13),

	LRI(44, POSTED),

	REG(0x28),

	REG(0x9c),

	REG(0xc0),

	REG(0x178),

	REG(0x17c),

	REG16(0x358),

	REG(0x170),

	REG(0x150),

	REG(0x154),

	REG(0x158),

	REG16(0x41c),

	REG16(0x600),

	REG16(0x604),

	REG16(0x608),

	REG16(0x60c),

	REG16(0x610),

	REG16(0x614),

	REG16(0x618),

	REG16(0x61c),

	REG16(0x620),

	REG16(0x624),

	REG16(0x628),

	REG16(0x62c),

	REG16(0x630),

	REG16(0x634),

	REG16(0x638),

	REG16(0x63c),

	REG16(0x640),

	REG16(0x644),

	REG16(0x648),

	REG16(0x64c),

	REG16(0x650),

	REG16(0x654),

	REG16(0x658),

	REG16(0x65c),

	REG16(0x660),

	REG16(0x664),

	REG16(0x668),

	REG16(0x66c),

	REG16(0x670),

	REG16(0x674),

	REG16(0x678),

	REG16(0x67c),

	REG(0x68),



	END()

};



static const u8 gen11_rcs_offsets[] = {

	NOP(1),

	LRI(15, POSTED),
@@ -832,6 +916,8 @@ static const u8 *reg_offsets(const struct intel_engine_cs *engine) 
			return gen12_rcs_offsets;

		else if (INTEL_GEN(engine->i915) >= 11)

			return gen11_rcs_offsets;

		else if (INTEL_GEN(engine->i915) >= 9)

			return gen9_rcs_offsets;

		else

			return gen8_rcs_offsets;

	} else {

drivers/gpu/drm/i915/gt/selftest_lrc.c

+7 −0
Original line number Diff line number Diff line
@@ -3406,6 +3406,13 @@ static int live_lrc_layout(void *arg) 
				continue;

			}



			if (lrc[dw] == 0) {

				pr_debug("%s: skipped instruction %x at dword %d\n",

					 engine->name, lri, dw);

				dw++;

				continue;

			}



			if ((lri & GENMASK(31, 23)) != MI_INSTR(0x22, 0)) {

				pr_err("%s: Expected LRI command at dword %d, found %08x\n",

				       engine->name, dw, lri);

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