Commit 6a45a658 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'x86-urgent-2020-06-11' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 

Pull more x86 updates from Thomas Gleixner:
 "A set of fixes and updates for x86:

   - Unbreak paravirt VDSO clocks.

     While the VDSO code was moved into lib for sharing a subtle check
     for the validity of paravirt clocks got replaced. While the
     replacement works perfectly fine for bare metal as the update of
     the VDSO clock mode is synchronous, it fails for paravirt clocks
     because the hypervisor can invalidate them asynchronously.

     Bring it back as an optional function so it does not inflict this
     on architectures which are free of PV damage.

   - Fix the jiffies to jiffies64 mapping on 64bit so it does not
     trigger an ODR violation on newer compilers

   - Three fixes for the SSBD and *IB* speculation mitigation maze to
     ensure consistency, not disabling of some *IB* variants wrongly and
     to prevent a rogue cross process shutdown of SSBD. All marked for
     stable.

   - Add yet more CPU models to the splitlock detection capable list
     !@#%$!

   - Bring the pr_info() back which tells that TSC deadline timer is
     enabled.

   - Reboot quirk for MacBook6,1"

* tag 'x86-urgent-2020-06-11' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  x86/vdso: Unbreak paravirt VDSO clocks
  lib/vdso: Provide sanity check for cycles (again)
  clocksource: Remove obsolete ifdef
  x86_64: Fix jiffies ODR violation
  x86/speculation: PR_SPEC_FORCE_DISABLE enforcement for indirect branches.
  x86/speculation: Prevent rogue cross-process SSBD shutdown
  x86/speculation: Avoid force-disabling IBPB based on STIBP and enhanced IBRS.
  x86/cpu: Add Sapphire Rapids CPU model number
  x86/split_lock: Add Icelake microserver and Tigerlake CPU models
  x86/apic: Make TSC deadline timer detection message visible
  x86/reboot/quirks: Add MacBook6,1 reboot quirk
parents 92ac9712 7778d841

arch/x86/include/asm/intel-family.h

+2 −0
Original line number Diff line number Diff line
@@ -89,6 +89,8 @@ 
#define INTEL_FAM6_COMETLAKE		0xA5

#define INTEL_FAM6_COMETLAKE_L		0xA6



#define INTEL_FAM6_SAPPHIRERAPIDS_X	0x8F



/* "Small Core" Processors (Atom) */



#define INTEL_FAM6_ATOM_BONNELL		0x1C /* Diamondville, Pineview */

arch/x86/include/asm/vdso/gettimeofday.h

+18 −0
Original line number Diff line number Diff line
@@ -271,6 +271,24 @@ static __always_inline const struct vdso_data *__arch_get_vdso_data(void) 
	return __vdso_data;

}



static inline bool arch_vdso_clocksource_ok(const struct vdso_data *vd)

{

	return true;

}

#define vdso_clocksource_ok arch_vdso_clocksource_ok



/*

 * Clocksource read value validation to handle PV and HyperV clocksources

 * which can be invalidated asynchronously and indicate invalidation by

 * returning U64_MAX, which can be effectively tested by checking for a

 * negative value after casting it to s64.

 */

static inline bool arch_vdso_cycles_ok(u64 cycles)

{

	return (s64)cycles >= 0;

}

#define vdso_cycles_ok arch_vdso_cycles_ok



/*

 * x86 specific delta calculation.

 *

arch/x86/kernel/apic/apic.c

+1 −1
Original line number Diff line number Diff line
@@ -2060,7 +2060,7 @@ void __init init_apic_mappings(void) 
	unsigned int new_apicid;



	if (apic_validate_deadline_timer())

		pr_debug("TSC deadline timer available\n");

		pr_info("TSC deadline timer available\n");



	if (x2apic_mode) {

		boot_cpu_physical_apicid = read_apic_id();

arch/x86/kernel/cpu/bugs.c

+54 −38
Original line number Diff line number Diff line
@@ -588,7 +588,9 @@ early_param("nospectre_v1", nospectre_v1_cmdline); 
static enum spectre_v2_mitigation spectre_v2_enabled __ro_after_init =

	SPECTRE_V2_NONE;



static enum spectre_v2_user_mitigation spectre_v2_user __ro_after_init =

static enum spectre_v2_user_mitigation spectre_v2_user_stibp __ro_after_init =

	SPECTRE_V2_USER_NONE;

static enum spectre_v2_user_mitigation spectre_v2_user_ibpb __ro_after_init =

	SPECTRE_V2_USER_NONE;



#ifdef CONFIG_RETPOLINE
@@ -734,15 +736,6 @@ spectre_v2_user_select_mitigation(enum spectre_v2_mitigation_cmd v2_cmd) 
		break;

	}



	/*

	 * At this point, an STIBP mode other than "off" has been set.

	 * If STIBP support is not being forced, check if STIBP always-on

	 * is preferred.

	 */

	if (mode != SPECTRE_V2_USER_STRICT &&

	    boot_cpu_has(X86_FEATURE_AMD_STIBP_ALWAYS_ON))

		mode = SPECTRE_V2_USER_STRICT_PREFERRED;



	/* Initialize Indirect Branch Prediction Barrier */

	if (boot_cpu_has(X86_FEATURE_IBPB)) {

		setup_force_cpu_cap(X86_FEATURE_USE_IBPB);
@@ -765,22 +758,35 @@ spectre_v2_user_select_mitigation(enum spectre_v2_mitigation_cmd v2_cmd) 
		pr_info("mitigation: Enabling %s Indirect Branch Prediction Barrier\n",

			static_key_enabled(&switch_mm_always_ibpb) ?

			"always-on" : "conditional");



		spectre_v2_user_ibpb = mode;

	}



	/* If enhanced IBRS is enabled no STIBP required */

	if (spectre_v2_enabled == SPECTRE_V2_IBRS_ENHANCED)

	/*

	 * If enhanced IBRS is enabled or SMT impossible, STIBP is not

	 * required.

	 */

	if (!smt_possible || spectre_v2_enabled == SPECTRE_V2_IBRS_ENHANCED)

		return;



	/*

	 * If SMT is not possible or STIBP is not available clear the STIBP

	 * mode.

	 * At this point, an STIBP mode other than "off" has been set.

	 * If STIBP support is not being forced, check if STIBP always-on

	 * is preferred.

	 */

	if (!smt_possible || !boot_cpu_has(X86_FEATURE_STIBP))

	if (mode != SPECTRE_V2_USER_STRICT &&

	    boot_cpu_has(X86_FEATURE_AMD_STIBP_ALWAYS_ON))

		mode = SPECTRE_V2_USER_STRICT_PREFERRED;



	/*

	 * If STIBP is not available, clear the STIBP mode.

	 */

	if (!boot_cpu_has(X86_FEATURE_STIBP))

		mode = SPECTRE_V2_USER_NONE;



	spectre_v2_user_stibp = mode;



set_mode:

	spectre_v2_user = mode;

	/* Only print the STIBP mode when SMT possible */

	if (smt_possible)

	pr_info("%s\n", spectre_v2_user_strings[mode]);

}
@@ -1014,7 +1020,7 @@ void cpu_bugs_smt_update(void) 
{

	mutex_lock(&spec_ctrl_mutex);



	switch (spectre_v2_user) {

	switch (spectre_v2_user_stibp) {

	case SPECTRE_V2_USER_NONE:

		break;

	case SPECTRE_V2_USER_STRICT:
@@ -1257,14 +1263,19 @@ static int ib_prctl_set(struct task_struct *task, unsigned long ctrl) 
{

	switch (ctrl) {

	case PR_SPEC_ENABLE:

		if (spectre_v2_user == SPECTRE_V2_USER_NONE)

		if (spectre_v2_user_ibpb == SPECTRE_V2_USER_NONE &&

		    spectre_v2_user_stibp == SPECTRE_V2_USER_NONE)

			return 0;

		/*

		 * Indirect branch speculation is always disabled in strict

		 * mode.

		 * mode. It can neither be enabled if it was force-disabled

		 * by a  previous prctl call.



		 */

		if (spectre_v2_user == SPECTRE_V2_USER_STRICT ||

		    spectre_v2_user == SPECTRE_V2_USER_STRICT_PREFERRED)

		if (spectre_v2_user_ibpb == SPECTRE_V2_USER_STRICT ||

		    spectre_v2_user_stibp == SPECTRE_V2_USER_STRICT ||

		    spectre_v2_user_stibp == SPECTRE_V2_USER_STRICT_PREFERRED ||

		    task_spec_ib_force_disable(task))

			return -EPERM;

		task_clear_spec_ib_disable(task);

		task_update_spec_tif(task);
@@ -1275,10 +1286,12 @@ static int ib_prctl_set(struct task_struct *task, unsigned long ctrl) 
		 * Indirect branch speculation is always allowed when

		 * mitigation is force disabled.

		 */

		if (spectre_v2_user == SPECTRE_V2_USER_NONE)

		if (spectre_v2_user_ibpb == SPECTRE_V2_USER_NONE &&

		    spectre_v2_user_stibp == SPECTRE_V2_USER_NONE)

			return -EPERM;

		if (spectre_v2_user == SPECTRE_V2_USER_STRICT ||

		    spectre_v2_user == SPECTRE_V2_USER_STRICT_PREFERRED)

		if (spectre_v2_user_ibpb == SPECTRE_V2_USER_STRICT ||

		    spectre_v2_user_stibp == SPECTRE_V2_USER_STRICT ||

		    spectre_v2_user_stibp == SPECTRE_V2_USER_STRICT_PREFERRED)

			return 0;

		task_set_spec_ib_disable(task);

		if (ctrl == PR_SPEC_FORCE_DISABLE)
@@ -1309,7 +1322,8 @@ void arch_seccomp_spec_mitigate(struct task_struct *task) 
{

	if (ssb_mode == SPEC_STORE_BYPASS_SECCOMP)

		ssb_prctl_set(task, PR_SPEC_FORCE_DISABLE);

	if (spectre_v2_user == SPECTRE_V2_USER_SECCOMP)

	if (spectre_v2_user_ibpb == SPECTRE_V2_USER_SECCOMP ||

	    spectre_v2_user_stibp == SPECTRE_V2_USER_SECCOMP)

		ib_prctl_set(task, PR_SPEC_FORCE_DISABLE);

}

#endif
@@ -1340,23 +1354,25 @@ static int ib_prctl_get(struct task_struct *task) 
	if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2))

		return PR_SPEC_NOT_AFFECTED;



	switch (spectre_v2_user) {

	case SPECTRE_V2_USER_NONE:

	if (spectre_v2_user_ibpb == SPECTRE_V2_USER_NONE &&

	    spectre_v2_user_stibp == SPECTRE_V2_USER_NONE)

		return PR_SPEC_ENABLE;

	case SPECTRE_V2_USER_PRCTL:

	case SPECTRE_V2_USER_SECCOMP:

	else if (spectre_v2_user_ibpb == SPECTRE_V2_USER_STRICT ||

	    spectre_v2_user_stibp == SPECTRE_V2_USER_STRICT ||

	    spectre_v2_user_stibp == SPECTRE_V2_USER_STRICT_PREFERRED)

		return PR_SPEC_DISABLE;

	else if (spectre_v2_user_ibpb == SPECTRE_V2_USER_PRCTL ||

	    spectre_v2_user_ibpb == SPECTRE_V2_USER_SECCOMP ||

	    spectre_v2_user_stibp == SPECTRE_V2_USER_PRCTL ||

	    spectre_v2_user_stibp == SPECTRE_V2_USER_SECCOMP) {

		if (task_spec_ib_force_disable(task))

			return PR_SPEC_PRCTL | PR_SPEC_FORCE_DISABLE;

		if (task_spec_ib_disable(task))

			return PR_SPEC_PRCTL | PR_SPEC_DISABLE;

		return PR_SPEC_PRCTL | PR_SPEC_ENABLE;

	case SPECTRE_V2_USER_STRICT:

	case SPECTRE_V2_USER_STRICT_PREFERRED:

		return PR_SPEC_DISABLE;

	default:

	} else

		return PR_SPEC_NOT_AFFECTED;

}

}



int arch_prctl_spec_ctrl_get(struct task_struct *task, unsigned long which)

{
@@ -1594,7 +1610,7 @@ static char *stibp_state(void) 
	if (spectre_v2_enabled == SPECTRE_V2_IBRS_ENHANCED)

		return "";



	switch (spectre_v2_user) {

	switch (spectre_v2_user_stibp) {

	case SPECTRE_V2_USER_NONE:

		return ", STIBP: disabled";

	case SPECTRE_V2_USER_STRICT:

arch/x86/kernel/cpu/intel.c

+3 −0
Original line number Diff line number Diff line
@@ -1142,9 +1142,12 @@ void switch_to_sld(unsigned long tifn) 
static const struct x86_cpu_id split_lock_cpu_ids[] __initconst = {

	X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_X,		0),

	X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_L,		0),

	X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_D,		0),

	X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT,	1),

	X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT_D,	1),

	X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT_L,	1),

	X86_MATCH_INTEL_FAM6_MODEL(TIGERLAKE_L,		1),

	X86_MATCH_INTEL_FAM6_MODEL(TIGERLAKE,		1),

	{}

};

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