bus: ti-sysc: Fix wrong offset for display subsystem reset quirk (69e60903) · Commits · 戴 / test

Commit ("bus: ti-sysc: Implement display subsystem reset quirk") added support for DSS reset, but is using dispc offset also for DSS also registers as reported by Tomi Valkeinen <tomi.valkeinen@ti.com>. Also, we're not using dispc_offset for dispc IRQSTATUS register so let's fix that too. Fixes: ("bus: ti-sysc: Implement display subsystem reset quirk") Reported-by:

Tomi Valkeinen <tomi.valkeinen@ti.com> Reviewed-by:

Tomi Valkeinen <tomi.valkeinen@ti.com> Signed-off-by:

Tony Lindgren <tony@atomide.com>

drivers/bus/ti-sysc.c

+4 −4

Original line number	Diff line number	Diff line
		@@ -1566,7 +1566,7 @@ static void sysc_pre_reset_quirk_dss(struct sysc *ddata)
		return;

		/* Clear IRQSTATUS */
		sysc_write(ddata, 0x1000 + 0x18, irq_mask);
		sysc_write(ddata, dispc_offset + 0x18, irq_mask);

		/* Disable outputs */
		val = sysc_quirk_dispc(ddata, dispc_offset, true);
		@@ -1580,14 +1580,14 @@ static void sysc_pre_reset_quirk_dss(struct sysc *ddata)

		if (sysc_soc->soc == SOC_3430) {
		/* Clear DSS_SDI_CONTROL */
		sysc_write(ddata, dispc_offset + 0x44, 0);
		sysc_write(ddata, 0x44, 0);

		/* Clear DSS_PLL_CONTROL */
		sysc_write(ddata, dispc_offset + 0x48, 0);
		sysc_write(ddata, 0x48, 0);
		}

		/* Clear DSS_CONTROL to switch DSS clock sources to PRCM if not */
		sysc_write(ddata, dispc_offset + 0x40, 0);
		sysc_write(ddata, 0x40, 0);
		}

		/* 1-wire needs module's internal clocks enabled for reset */

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