Commit 69cc1502 authored by Krzysztof Kozlowski's avatar Krzysztof Kozlowski Committed by Shawn Guo
Browse files

ARM: dts: imx: Align L2 cache-controller nodename with dtschema



Fix dtschema validator warnings like:
    l2-cache@a02000: $nodename:0:
        'l2-cache@a02000' does not match '^(cache-controller|cpu)(@[0-9a-f,]+)*$'

Signed-off-by: default avatarKrzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent 954809fb
Loading
Loading
Loading
Loading
+1 −1
Original line number Diff line number Diff line
@@ -59,7 +59,7 @@
		interrupt-parent = <&avic>;
		ranges;

		L2: l2-cache@30000000 {
		L2: cache-controller@30000000 {
			compatible = "arm,l210-cache";
			reg = <0x30000000 0x1000>;
			cache-unified;
+1 −1
Original line number Diff line number Diff line
@@ -245,7 +245,7 @@
			interrupt-parent = <&intc>;
		};

		L2: l2-cache@a02000 {
		L2: cache-controller@a02000 {
			compatible = "arm,pl310-cache";
			reg = <0x00a02000 0x1000>;
			interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
+1 −1
Original line number Diff line number Diff line
@@ -126,7 +126,7 @@
			interrupt-parent = <&intc>;
		};

		L2: l2-cache@a02000 {
		L2: cache-controller@a02000 {
			compatible = "arm,pl310-cache";
			reg = <0x00a02000 0x1000>;
			interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
+1 −1
Original line number Diff line number Diff line
@@ -126,7 +126,7 @@
			interrupt-parent = <&intc>;
		};

		L2: l2-cache@a02000 {
		L2: cache-controller@a02000 {
			compatible = "arm,pl310-cache";
			reg = <0x00a02000 0x1000>;
			interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
+1 −1
Original line number Diff line number Diff line
@@ -179,7 +179,7 @@
			interrupt-parent = <&intc>;
		};

		L2: l2-cache@a02000 {
		L2: cache-controller@a02000 {
			compatible = "arm,pl310-cache";
			reg = <0x00a02000 0x1000>;
			interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;