Commit 69c32972 authored by Kulkarni, Ganapatrao's avatar Kulkarni, Ganapatrao Committed by Will Deacon
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drivers/perf: Add Cavium ThunderX2 SoC UNCORE PMU driver



This patch adds a perf driver for the PMU UNCORE devices DDR4 Memory
Controller(DMC) and Level 3 Cache(L3C). Each PMU supports up to 4
counters. All counters lack overflow interrupt and are
sampled periodically.

Reviewed-by: default avatarSuzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: default avatarGanapatrao Kulkarni <ganapatrao.kulkarni@cavium.com>
[will: consistent enum cpuhp_state naming]
Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
parent d6310a3f
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@@ -87,6 +87,15 @@ config QCOM_L3_PMU
	   Adds the L3 cache PMU into the perf events subsystem for
	   monitoring L3 cache events.

config THUNDERX2_PMU
	tristate "Cavium ThunderX2 SoC PMU UNCORE"
	depends on ARCH_THUNDER2 && ARM64 && ACPI && NUMA
	default m
	help
	   Provides support for ThunderX2 UNCORE events.
	   The SoC has PMU support in its L3 cache controller (L3C) and
	   in the DDR4 Memory Controller (DMC).

config XGENE_PMU
        depends on ARCH_XGENE
        bool "APM X-Gene SoC PMU"
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@@ -7,5 +7,6 @@ obj-$(CONFIG_ARM_PMU_ACPI) += arm_pmu_acpi.o
obj-$(CONFIG_HISI_PMU) += hisilicon/
obj-$(CONFIG_QCOM_L2_PMU)	+= qcom_l2_pmu.o
obj-$(CONFIG_QCOM_L3_PMU) += qcom_l3_pmu.o
obj-$(CONFIG_THUNDERX2_PMU) += thunderx2_pmu.o
obj-$(CONFIG_XGENE_PMU) += xgene_pmu.o
obj-$(CONFIG_ARM_SPE_PMU) += arm_spe_pmu.o
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@@ -165,6 +165,7 @@ enum cpuhp_state {
	CPUHP_AP_PERF_ARM_QCOM_L2_ONLINE,
	CPUHP_AP_PERF_ARM_QCOM_L3_ONLINE,
	CPUHP_AP_PERF_ARM_APM_XGENE_ONLINE,
	CPUHP_AP_PERF_ARM_CAVIUM_TX2_UNCORE_ONLINE,
	CPUHP_AP_PERF_POWERPC_NEST_IMC_ONLINE,
	CPUHP_AP_PERF_POWERPC_CORE_IMC_ONLINE,
	CPUHP_AP_PERF_POWERPC_THREAD_IMC_ONLINE,