dt-bindings: PCI: cadence: Add PCIe RC/EP DT schema for Cadence PCIe

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: "http://devicetree.org/schemas/pci/cdns-pcie-host.yaml#"

$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Cadence PCIe Host

maintainers:

  - Tom Joseph <tjoseph@cadence.com>

allOf:

  - $ref: "/schemas/pci/pci-bus.yaml#"

  - $ref: "cdns-pcie.yaml#"

properties:

  cdns,no-bar-match-nbits:

    description:

      Set into the no BAR match register to configure the number of least

      significant bits kept during inbound (PCIe -> AXI) address translations

    allOf:

      - $ref: /schemas/types.yaml#/definitions/uint32

    minimum: 0

    maximum: 64

    default: 32

  msi-parent: true

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: "http://devicetree.org/schemas/pci/cdns-pcie.yaml#"

$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Cadence PCIe Core

maintainers:

  - Tom Joseph <tjoseph@cadence.com>

properties:

  cdns,max-outbound-regions:

    description: maximum number of outbound regions

    allOf:

      - $ref: /schemas/types.yaml#/definitions/uint32

    minimum: 1

    maximum: 32

    default: 32

  phys:

    description:

      One per lane if more than one in the list. If only one PHY listed it must

      manage all lanes.

    minItems: 1

    maxItems: 16

  phy-names:

    items:

      - const: pcie-phy

    # FIXME: names when more than 1