Commit 6921e58b authored by Kishon Vijay Abraham I's avatar Kishon Vijay Abraham I Committed by Tony Lindgren
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ARM: dts: dra7: Use "syscon-phy-power" and "syscon-pcs" in PCIe PHY node 



Add "syscon-phy-power" property and "syscon-pcs" property which can
be used to perform the control module initializations and remove
the deprecated "ctrl-module" property from PCIe PHY dt nodes.

Phandle to "sysclk" clock node is also added to the PCIe PHY node
since some of the syscon initializations is based on system clock
frequency.

Since "omap_control_pcie1phy" and "omap_control_pcie2phy" devicetree
nodes are no longer used, remove it.

Signed-off-by: default avatarKishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
parent 43acf169

arch/arm/boot/dts/dra7.dtsi

+10 −23
Original line number Original line Diff line number Diff line
@@ -1207,16 +1207,18 @@ 
				reg = <0x4a094000 0x80>, /* phy_rx */

				reg = <0x4a094000 0x80>, /* phy_rx */

				      <0x4a094400 0x64>; /* phy_tx */

				      <0x4a094400 0x64>; /* phy_tx */

				reg-names = "phy_rx", "phy_tx";

				reg-names = "phy_rx", "phy_tx";

				ctrl-module = <&omap_control_pcie1phy>;

				syscon-phy-power = <&scm_conf_pcie 0x1c>;

				syscon-pcs = <&scm_conf_pcie 0x10>;

				clocks = <&dpll_pcie_ref_ck>,

				clocks = <&dpll_pcie_ref_ck>,

					 <&dpll_pcie_ref_m2ldo_ck>,

					 <&dpll_pcie_ref_m2ldo_ck>,

					 <&optfclk_pciephy1_32khz>,

					 <&optfclk_pciephy1_32khz>,

					 <&optfclk_pciephy1_clk>,

					 <&optfclk_pciephy1_clk>,

					 <&optfclk_pciephy1_div_clk>,

					 <&optfclk_pciephy1_div_clk>,

					 <&optfclk_pciephy_div>;

					 <&optfclk_pciephy_div>,

					 <&sys_clkin1>;

				clock-names = "dpll_ref", "dpll_ref_m2",

				clock-names = "dpll_ref", "dpll_ref_m2",

					      "wkupclk", "refclk",

					      "wkupclk", "refclk",

					      "div-clk", "phy-div";

					      "div-clk", "phy-div", "sysclk";

				#phy-cells = <0>;

				#phy-cells = <0>;

			};

			};
@@ -1225,16 +1227,18 @@ 
				reg = <0x4a095000 0x80>, /* phy_rx */

				reg = <0x4a095000 0x80>, /* phy_rx */

				      <0x4a095400 0x64>; /* phy_tx */

				      <0x4a095400 0x64>; /* phy_tx */

				reg-names = "phy_rx", "phy_tx";

				reg-names = "phy_rx", "phy_tx";

				ctrl-module = <&omap_control_pcie2phy>;

				syscon-phy-power = <&scm_conf_pcie 0x20>;

				syscon-pcs = <&scm_conf_pcie 0x10>;

				clocks = <&dpll_pcie_ref_ck>,

				clocks = <&dpll_pcie_ref_ck>,

					 <&dpll_pcie_ref_m2ldo_ck>,

					 <&dpll_pcie_ref_m2ldo_ck>,

					 <&optfclk_pciephy2_32khz>,

					 <&optfclk_pciephy2_32khz>,

					 <&optfclk_pciephy2_clk>,

					 <&optfclk_pciephy2_clk>,

					 <&optfclk_pciephy2_div_clk>,

					 <&optfclk_pciephy2_div_clk>,

					 <&optfclk_pciephy_div>;

					 <&optfclk_pciephy_div>,

					 <&sys_clkin1>;

				clock-names = "dpll_ref", "dpll_ref_m2",

				clock-names = "dpll_ref", "dpll_ref_m2",

					      "wkupclk", "refclk",

					      "wkupclk", "refclk",

					      "div-clk", "phy-div";

					      "div-clk", "phy-div", "sysclk";

				#phy-cells = <0>;

				#phy-cells = <0>;

				status = "disabled";

				status = "disabled";

			};

			};
@@ -1250,23 +1254,6 @@ 
			ti,hwmods = "sata";

			ti,hwmods = "sata";

		};

		};





		omap_control_pcie1phy: control-phy@0x4a003c40 {

			compatible = "ti,control-phy-pcie";

			reg = <0x4a003c40 0x4>, <0x4a003c14 0x4>, <0x4a003c34 0x4>;

			reg-names = "power", "control_sma", "pcie_pcs";

			clocks = <&sys_clkin1>;

			clock-names = "sysclk";

		};



		omap_control_pcie2phy: control-pcie@0x4a003c44 {

			compatible = "ti,control-phy-pcie";

			reg = <0x4a003c44 0x4>, <0x4a003c14 0x4>, <0x4a003c34 0x4>;

			reg-names = "power", "control_sma", "pcie_pcs";

			clocks = <&sys_clkin1>;

			clock-names = "sysclk";

			status = "disabled";

		};



		rtc: rtc@48838000 {

		rtc: rtc@48838000 {

			compatible = "ti,am3352-rtc";

			compatible = "ti,am3352-rtc";

			reg = <0x48838000 0x100>;

			reg = <0x48838000 0x100>;

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