Commit 690677c2 authored by Andreas Färber's avatar Andreas Färber
Browse files

arm64: dts: realtek: rtd129x: Use reserved-memory for RPC regions 



Move /reserved-memory node from RTD1295 to RTD129x DT.
Convert RPC /memreserve/s into /reserved-memory nodes.

Fixes: 72a7786c ("ARM64: dts: Add Realtek RTD1295 and Zidoo X9S")
Fixes: f8b3436d ("arm64: dts: realtek: Factor out common RTD129x parts")
Signed-off-by: default avatarAndreas Färber <afaerber@suse.de>
parent 31888c8b

arch/arm64/boot/dts/realtek/rtd1295.dtsi

+1 −12
Original line number Diff line number Diff line
@@ -2,7 +2,7 @@ 
/*

 * Realtek RTD1295 SoC

 *

 * Copyright (c) 2016-2017 Andreas Färber

 * Copyright (c) 2016-2019 Andreas Färber

 */



#include "rtd129x.dtsi"
@@ -47,17 +47,6 @@ 
		};

	};



	reserved-memory {

		#address-cells = <1>;

		#size-cells = <1>;

		ranges;



		tee@10100000 {

			reg = <0x10100000 0xf00000>;

			no-map;

		};

	};



	timer {

		compatible = "arm,armv8-timer";

		interrupts = <GIC_PPI 13

arch/arm64/boot/dts/realtek/rtd129x.dtsi

+20 −3
Original line number Diff line number Diff line
@@ -2,14 +2,12 @@ 
/*

 * Realtek RTD1293/RTD1295/RTD1296 SoC

 *

 * Copyright (c) 2016-2017 Andreas Färber

 * Copyright (c) 2016-2019 Andreas Färber

 */



/memreserve/	0x0000000000000000 0x0000000000030000;

/memreserve/	0x000000000001f000 0x0000000000001000;

/memreserve/	0x0000000000030000 0x00000000000d0000;

/memreserve/	0x0000000001b00000 0x00000000004be000;

/memreserve/	0x0000000001ffe000 0x0000000000004000;



#include <dt-bindings/interrupt-controller/arm-gic.h>

#include <dt-bindings/reset/realtek,rtd1295.h>
@@ -19,6 +17,25 @@ 
	#address-cells = <1>;

	#size-cells = <1>;



	reserved-memory {

		#address-cells = <1>;

		#size-cells = <1>;

		ranges;



		rpc_comm: rpc@1f000 {

			reg = <0x1f000 0x1000>;

		};



		rpc_ringbuf: rpc@1ffe000 {

			reg = <0x1ffe000 0x4000>;

		};



		tee: tee@10100000 {

			reg = <0x10100000 0xf00000>;

			no-map;

		};

	};



	arm_pmu: arm-pmu {

		compatible = "arm,cortex-a53-pmu";

		interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;

CRA Git | Maintained and supported by SUSTech CRA and CCSE