Commit 68e2fc78 authored by Michael Hennerich's avatar Michael Hennerich Committed by Bryan Wu
Browse files

Blackfin arch: Fix bug - Kernel does not boot if re-program clocks 



Don't write conflicting data to EBIU_SDBCTL after the SDRAM is
configured. This can cause data corruption, since we might change SDRAM
row and column addressing modes.

Signed-off-by: default avatarMichael Hennerich <michael.hennerich@analog.com>
Signed-off-by: default avatarBryan Wu <cooloney@kernel.org>
parent 260d5d35

arch/blackfin/Kconfig

+0 −14
Original line number Diff line number Diff line
@@ -315,20 +315,6 @@ config MEM_SIZE 
	depends on BFIN_KERNEL_CLOCK

	default 64



config MEM_ADD_WIDTH

	int "Memory Address Width"

	depends on BFIN_KERNEL_CLOCK

	depends on (!BF54x)

	range 8 11

	default  9 if BFIN533_EZKIT

	default  9 if BFIN561_EZKIT

	default  9 if H8606_HVSISTEMAS

	default 10 if BFIN527_EZKIT

	default 10 if BFIN537_STAMP

	default 11 if BFIN533_STAMP

	default 10 if PNAV10

	default 10 if BFIN532_IP0X



config PLL_BYPASS

	bool "Bypass PLL"

	depends on BFIN_KERNEL_CLOCK

arch/blackfin/mach-bf527/head.S

+3 −9
Original line number Diff line number Diff line
@@ -32,7 +32,7 @@ 
#include <asm/blackfin.h>

#include <asm/trace.h>



#if CONFIG_BFIN_KERNEL_CLOCK

#ifdef CONFIG_BFIN_KERNEL_CLOCK

#include <asm/mach-common/clocks.h>

#include <asm/mach/mem_init.h>

#endif
@@ -185,7 +185,7 @@ ENTRY(__start) 


	/* Put The Code for PLL Programming and SDRAM Programming in L1 ISRAM */

	call _bf53x_relocate_l1_mem;

#if CONFIG_BFIN_KERNEL_CLOCK

#ifdef CONFIG_BFIN_KERNEL_CLOCK

	call _start_dma_code;

#endif
@@ -318,7 +318,7 @@ ENDPROC(_real_start) 
__FINIT



.section .l1.text

#if CONFIG_BFIN_KERNEL_CLOCK

#ifdef CONFIG_BFIN_KERNEL_CLOCK

ENTRY(_start_dma_code)



	/* Enable PHY CLK buffer output */
@@ -398,12 +398,6 @@ ENTRY(_start_dma_code) 
	w[p0] = r0.l;

	ssync;



	p0.l = LO(EBIU_SDBCTL);

	p0.h = HI(EBIU_SDBCTL);     /* SDRAM Memory Bank Control Register */

	r0 = mem_SDBCTL;

	w[p0] = r0.l;

	ssync;



	P2.H = hi(EBIU_SDGCTL);

	P2.L = lo(EBIU_SDGCTL);

	R0 = [P2];

arch/blackfin/mach-bf533/head.S

+3 −9
Original line number Diff line number Diff line
@@ -31,7 +31,7 @@ 
#include <linux/init.h>

#include <asm/blackfin.h>

#include <asm/trace.h>

#if CONFIG_BFIN_KERNEL_CLOCK

#ifdef CONFIG_BFIN_KERNEL_CLOCK

#include <asm/mach-common/clocks.h>

#include <asm/mach/mem_init.h>

#endif
@@ -186,7 +186,7 @@ ENTRY(__start) 


	/* Put The Code for PLL Programming and SDRAM Programming in L1 ISRAM */

	call _bf53x_relocate_l1_mem;

#if CONFIG_BFIN_KERNEL_CLOCK

#ifdef CONFIG_BFIN_KERNEL_CLOCK

	call _start_dma_code;

#endif
@@ -319,7 +319,7 @@ ENDPROC(_real_start) 
__FINIT



.section .l1.text

#if CONFIG_BFIN_KERNEL_CLOCK

#ifdef CONFIG_BFIN_KERNEL_CLOCK

ENTRY(_start_dma_code)

	p0.h = hi(SIC_IWR);

	p0.l = lo(SIC_IWR);
@@ -390,12 +390,6 @@ ENTRY(_start_dma_code) 
	w[p0] = r0.l;

	ssync;



	p0.l = LO(EBIU_SDBCTL);

	p0.h = HI(EBIU_SDBCTL);     /* SDRAM Memory Bank Control Register */

	r0 = mem_SDBCTL;

	w[p0] = r0.l;

	ssync;



	P2.H = hi(EBIU_SDGCTL);

	P2.L = lo(EBIU_SDGCTL);

	R0 = [P2];

arch/blackfin/mach-bf537/head.S

+3 −9
Original line number Diff line number Diff line
@@ -32,7 +32,7 @@ 
#include <asm/blackfin.h>

#include <asm/trace.h>



#if CONFIG_BFIN_KERNEL_CLOCK

#ifdef CONFIG_BFIN_KERNEL_CLOCK

#include <asm/mach-common/clocks.h>

#include <asm/mach/mem_init.h>

#endif
@@ -217,7 +217,7 @@ ENTRY(__start) 


	/* Put The Code for PLL Programming and SDRAM Programming in L1 ISRAM */

	call _bf53x_relocate_l1_mem;

#if CONFIG_BFIN_KERNEL_CLOCK

#ifdef CONFIG_BFIN_KERNEL_CLOCK

	call _start_dma_code;

#endif
@@ -350,7 +350,7 @@ ENDPROC(_real_start) 
__FINIT



.section .l1.text

#if CONFIG_BFIN_KERNEL_CLOCK

#ifdef CONFIG_BFIN_KERNEL_CLOCK

ENTRY(_start_dma_code)



	/* Enable PHY CLK buffer output */
@@ -430,12 +430,6 @@ ENTRY(_start_dma_code) 
	w[p0] = r0.l;

	ssync;



	p0.l = LO(EBIU_SDBCTL);

	p0.h = HI(EBIU_SDBCTL);     /* SDRAM Memory Bank Control Register */

	r0 = mem_SDBCTL;

	w[p0] = r0.l;

	ssync;



	P2.H = hi(EBIU_SDGCTL);

	P2.L = lo(EBIU_SDGCTL);

	R0 = [P2];

arch/blackfin/mach-bf548/head.S

+3 −3
Original line number Diff line number Diff line
@@ -31,7 +31,7 @@ 
#include <linux/init.h>

#include <asm/blackfin.h>

#include <asm/trace.h>

#if CONFIG_BFIN_KERNEL_CLOCK

#ifdef CONFIG_BFIN_KERNEL_CLOCK

#include <asm/mach-common/clocks.h>

#include <asm/mach/mem_init.h>

#endif
@@ -130,7 +130,7 @@ ENTRY(__start) 


	/* Put The Code for PLL Programming and SDRAM Programming in L1 ISRAM */

	call _bf53x_relocate_l1_mem;

#if CONFIG_BFIN_KERNEL_CLOCK

#ifdef CONFIG_BFIN_KERNEL_CLOCK

	call _start_dma_code;

#endif

	/* Code for initializing Async memory banks */
@@ -288,7 +288,7 @@ ENDPROC(_real_start) 
__FINIT



.section .l1.text

#if CONFIG_BFIN_KERNEL_CLOCK

#ifdef CONFIG_BFIN_KERNEL_CLOCK

ENTRY(_start_dma_code)



	/* Enable PHY CLK buffer output */

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