Commit 68af4fa8 authored Dec 01, 2016 by Boris Brezillon Committed by Stephen Boyd Dec 08, 2016

clk: bcm2835: Avoid overwriting the div info when disabling a pll_div clk



bcm2835_pll_divider_off() is resetting the divider field in the A2W reg
to zero when disabling the clock.

Make sure we preserve this value by reading the previous a2w_reg value
first and ORing the result with A2W_PLL_CHANNEL_DISABLE.

Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Fixes: 41691b88 ("clk: bcm2835: Add support for programming the audio domain clocks")
Cc: <stable@vger.kernel.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>

parent 035cd485

drivers/clk/bcm/clk-bcm2835.c

+3 −1

Original line number	Diff line number	Diff line
		@@ -751,7 +751,9 @@ static void bcm2835_pll_divider_off(struct clk_hw *hw)
		cprman_write(cprman, data->cm_reg,
		(cprman_read(cprman, data->cm_reg) &
		~data->load_mask) \| data->hold_mask);
		cprman_write(cprman, data->a2w_reg, A2W_PLL_CHANNEL_DISABLE);
		cprman_write(cprman, data->a2w_reg,
		cprman_read(cprman, data->a2w_reg) \|
		A2W_PLL_CHANNEL_DISABLE);
		spin_unlock(&cprman->regs_lock);
		}

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