Commit 68acd859 authored by Pierre-Louis Bossart's avatar Pierre-Louis Bossart Committed by Vinod Koul
Browse files

soundwire: cadence_master: simplify bus clash interrupt clear 



The bus clash interrupts are generated when the status is one, and
also cleared by writing a one. It's overkill/useless to use an OR when
the bit is already set.

Signed-off-by: default avatarPierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Link: https://lore.kernel.org/r/20190725234032.21152-12-pierre-louis.bossart@linux.intel.com


Signed-off-by: default avatarVinod Koul <vkoul@kernel.org>
parent 0fc6041d

drivers/soundwire/cadence_master.c

+0 −2
Original line number Diff line number Diff line
@@ -578,7 +578,6 @@ irqreturn_t sdw_cdns_irq(int irq, void *dev_id) 
	if (int_status & CDNS_MCP_INT_CTRL_CLASH) {

		/* Slave is driving bit slot during control word */

		dev_err_ratelimited(cdns->dev, "Bus clash for control word\n");

		int_status |= CDNS_MCP_INT_CTRL_CLASH;

	}



	if (int_status & CDNS_MCP_INT_DATA_CLASH) {
@@ -587,7 +586,6 @@ irqreturn_t sdw_cdns_irq(int irq, void *dev_id) 
		 * ownership of data bits or Slave gone bonkers

		 */

		dev_err_ratelimited(cdns->dev, "Bus clash for data word\n");

		int_status |= CDNS_MCP_INT_DATA_CLASH;

	}



	if (int_status & CDNS_MCP_INT_SLAVE_MASK) {

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